From patchwork Mon Mar 27 02:46:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13188507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09EF5C761AF for ; Mon, 27 Mar 2023 02:47:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NU8FpHAVqrERmHWF2lHhGGqO7gwLBwyKYReW5Cbu+sc=; b=G8h5++V3F4pvpC AhlnEridBcN3A0cJTaYF5cZB4CZQNIPwMpGUzVVJahBqZBXstT48nkK+j1hNUvSkU+Vh2JAz7GLbc te4Jegl8WgWLNpWHmfCNOWyubcPCGSHnsLDvehW9JHoTSAdrVfGaq49znVULHv2ufyXj5yGLLC2DX iyoZnRCtP6nb15iSOZhQ9Ic8Ex29uCIrLHyBcmKKAiBdT9ljUOgJOWqC9oktxilU+JRZXcZzuDgy4 tFnk9/5dRGyB3krxEjE9SyzCMONmfZtYMa72/sLCwrSKjdfwKPUVTNT2mSUWsaF2gevlBZc/4pYVH RNsKef4Y4K5i0C1iP1vg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pgcsr-009Z2q-1I; Mon, 27 Mar 2023 02:46:57 +0000 Received: from out30-119.freemail.mail.aliyun.com ([115.124.30.119]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pgcsT-009Ysj-2m for linux-arm-kernel@lists.infradead.org; Mon, 27 Mar 2023 02:46:37 +0000 X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R171e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045192;MF=renyu.zj@linux.alibaba.com;NM=1;PH=DS;RN=17;SR=0;TI=SMTPD_---0VeeqFQN_1679885186; Received: from srmbuffer011165236051.sqa.net(mailfrom:renyu.zj@linux.alibaba.com fp:SMTPD_---0VeeqFQN_1679885186) by smtp.aliyun-inc.com; Mon, 27 Mar 2023 10:46:27 +0800 From: Jing Zhang To: John Garry , Ian Rogers , Will Deacon , James Clark , Mike Leach , Leo Yan , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Shuai Xue , Zhuo Song , Jing Zhang Subject: [PATCH RFC 4/4] perf vendor events: Add JSON metrics for Yitian 710 DDR Date: Mon, 27 Mar 2023 10:46:12 +0800 Message-Id: <1679885172-95021-5-git-send-email-renyu.zj@linux.alibaba.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1679885172-95021-1-git-send-email-renyu.zj@linux.alibaba.com> References: <1679885172-95021-1-git-send-email-renyu.zj@linux.alibaba.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230326_194634_068344_83C49886 X-CRM114-Status: GOOD ( 12.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add JSON metrics for T-HEAD Yitian 710 SoC DDR. Signed-off-by: Jing Zhang --- .../arm64/freescale/yitian710/sys/ali_drw.json | 373 +++++++++++++++++++++ .../arm64/freescale/yitian710/sys/metrics.json | 20 ++ tools/perf/pmu-events/jevents.py | 1 + 3 files changed, 394 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/metrics.json diff --git a/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json b/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json new file mode 100644 index 0000000..cb8694b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ali_drw.json @@ -0,0 +1,373 @@ +[ + { + "BriefDescription": "A Write or Read Op at HIF interface. 64B", + "ConfigCode": "0x0", + "EventName": "hif_rd_or_wr", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Write Op at HIF interface. 64B", + "ConfigCode": "0x1", + "EventName": "hif_wr", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Read Op at HIF interface. 64B", + "ConfigCode": "0x2", + "EventName": "hif_rd", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Read-Modify-Write Op at HIF interface. 64B", + "ConfigCode": "0x3", + "EventName": "hif_rmw", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A high priority Read at HIF interface. 64B", + "ConfigCode": "0x4", + "EventName": "hif_hi_pri_rd", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A write data cycle at DFI interface (to DRAM)", + "ConfigCode": "0x7", + "EventName": "dfi_wr_data_cycles", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A read data cycle at DFI interface (to DRAM).", + "ConfigCode": "0x8", + "EventName": "dfi_rd_data_cycles", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A high priority read becomes critical.", + "ConfigCode": "0x9", + "EventName": "hpr_xact_when_critical", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A low priority read becomes critical.", + "ConfigCode": "0xA", + "EventName": "lpr_xact_when_critical", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A write becomes critical.", + "ConfigCode": "0xB", + "EventName": "wr_xact_when_critical", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "An Activate (ACT) command to DRAM.", + "ConfigCode": "0xC", + "EventName": "op_is_activate", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Read or Write CAS command to DRAM.", + "ConfigCode": "0xD", + "EventName": "op_is_rd_or_wr", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "An ACT command for read to DRAM.", + "ConfigCode": "0xE", + "EventName": "op_is_rd_activate", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Read CAS command to DRAM.", + "ConfigCode": "0xF", + "EventName": "op_is_rd", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Write CAS command to DRAM.", + "ConfigCode": "0x10", + "EventName": "op_is_wr", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Masked Write command to DRAM.", + "ConfigCode": "0x11", + "EventName": "op_is_mwr", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Precharge (PRE) command to DRAM.", + "ConfigCode": "0x12", + "EventName": "op_is_precharge", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A PRE required by read or write.", + "ConfigCode": "0x13", + "EventName": "precharge_for_rdwr", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A PRE required by other conditions.", + "ConfigCode": "0x14", + "EventName": "precharge_for_other", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A read-write turnaround.", + "ConfigCode": "0x15", + "EventName": "rdwr_transitions", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A write combine (merge) in write data buffer.", + "ConfigCode": "0x16", + "EventName": "write_combine", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Write-After-Read hazard.", + "ConfigCode": "0x17", + "EventName": "war_hazard", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Read-After-Write hazard.", + "ConfigCode": "0x18", + "EventName": "raw_hazard", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A Write-After-Write hazard.", + "ConfigCode": "0x19", + "EventName": "waw_hazard", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "Rank0 enters self-refresh (SRE).", + "ConfigCode": "0x1A", + "EventName": "op_is_enter_selfref_rk0", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "Rank1 enters self-refresh (SRE).", + "ConfigCode": "0x1B", + "EventName": "op_is_enter_selfref_rk1", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "Rank2 enters self-refresh (SRE).", + "ConfigCode": "0x1C", + "EventName": "op_is_enter_selfref_rk2", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "Rank3 enters self-refresh (SRE).", + "ConfigCode": "0x1D", + "EventName": "op_is_enter_selfref_rk3", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "Rank0 enters power-down (PDE).", + "ConfigCode": "0x1E", + "EventName": "op_is_enter_powerdown_rk0", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "Rank1 enters power-down (PDE).", + "ConfigCode": "0x1F", + "EventName": "op_is_enter_powerdown_rk1", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "Rank2 enters power-down (PDE).", + "ConfigCode": "0x20", + "EventName": "op_is_enter_powerdown_rk2", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "Rank3 enters power-down (PDE).", + "ConfigCode": "0x21", + "EventName": "op_is_enter_powerdown_rk3", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A cycle that Rank0 stays in self-refresh mode.", + "ConfigCode": "0x26", + "EventName": "selfref_mode_rk0", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A cycle that Rank1 stays in self-refresh mode.", + "ConfigCode": "0x27", + "EventName": "selfref_mode_rk1", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A cycle that Rank2 stays in self-refresh mode.", + "ConfigCode": "0x28", + "EventName": "selfref_mode_rk2", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A cycle that Rank3 stays in self-refresh mode.", + "ConfigCode": "0x29", + "EventName": "selfref_mode_rk3", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "An auto-refresh (REF) command to DRAM.", + "ConfigCode": "0x2A", + "EventName": "op_is_refresh", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A critical REF command to DRAM.", + "ConfigCode": "0x2B", + "EventName": "op_is_crit_ref", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "An MRR or MRW command to DRAM.", + "ConfigCode": "0x2D", + "EventName": "op_is_load_mode", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A ZQCal command to DRAM.", + "ConfigCode": "0x2E", + "EventName": "op_is_zqcl", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "At least one entry in read queue reaches the visible window limit.", + "ConfigCode": "0x30", + "EventName": "visible_window_limit_reached_rd", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "At least one entry in write queue reaches the visible window limit.", + "ConfigCode": "0x31", + "EventName": "visible_window_limit_reached_wr", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A DQS Oscillator MPC command to DRAM.", + "ConfigCode": "0x34", + "EventName": "op_is_dqsosc_mpc", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A DQS Oscillator MRR command to DRAM.", + "ConfigCode": "0x35", + "EventName": "op_is_dqsosc_mrr", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A TCR (Temperature Compensated Refresh) MRR command to DRAM.", + "ConfigCode": "0x36", + "EventName": "op_is_tcr_mrr", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A ZQCal Start command to DRAM.", + "ConfigCode": "0x37", + "EventName": "op_is_zqstart", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A ZQCal Latch command to DRAM.", + "ConfigCode": "0x38", + "EventName": "op_is_zqlatch", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A packet at CHI TXREQ interface (request).", + "ConfigCode": "0x39", + "EventName": "chi_txreq", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A packet at CHI TXDAT interface (read data).", + "ConfigCode": "0x3A", + "EventName": "chi_txdat", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A packet at CHI RXDAT interface (write data).", + "ConfigCode": "0x3B", + "EventName": "chi_rxdat", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A packet at CHI RXRSP interface.", + "ConfigCode": "0x3C", + "EventName": "chi_rxrsp", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "A violation detected in TZC.", + "ConfigCode": "0x3D", + "EventName": "tsz_vio", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "BriefDescription": "The ddr cycle.", + "ConfigCode": "0x80", + "EventName": "cycle", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/metrics.json new file mode 100644 index 0000000..c14ecac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/metrics.json @@ -0,0 +1,20 @@ +[ + { + "MetricName": "ddr_read_bandwidth.all", + "BriefDescription": "The ddr read bandwidth(MB/s).", + "MetricGroup": "ddr", + "MetricExpr": "hif_rd * 64 / 1e6 / duration_time", + "ScaleUnit": "1MB/s", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + }, + { + "MetricName": "ddr_write_bandwidth.all", + "BriefDescription": "The ddr write bandwidth(MB/s).", + "MetricGroup": "ddr", + "MetricExpr": "(hif_wr + hif_rmw) * 64 / 1e6 / duration_time", + "ScaleUnit": "1MB/s", + "Unit": "yitian710_ddr", + "Compat": "ali_drw_yitian710" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 20ed492..8cfb4b6 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -257,6 +257,7 @@ class JsonEvent: 'cpu_core': 'cpu_core', 'cpu_atom': 'cpu_atom', 'cmn700': 'cmn700', + 'yitian710_ddr': 'yitian710_ddr', } return table[unit] if unit in table else f'uncore_{unit.lower()}'