| Message ID | 1715231698-451-2-git-send-email-shengjiu.wang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mp-evk: support bt-sco sound card | expand |
On Thu, May 9, 2024 at 8:36 AM Shengjiu Wang <shengjiu.wang@nxp.com> wrote: > > Initialize audio PLL1 as the parent clock for 8kHz series rates, > audio PLL2 as the parent clock for 11kHz series rates. that PLL1 > and PLL2 can together support full range of audio sample rates. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index b92abb5a5c53..459c4a54d30e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1579,6 +1579,9 @@ audio_blk_ctrl: clock-controller@30e20000 { "sai1", "sai2", "sai3", "sai5", "sai6", "sai7"; power-domains = <&pgc_audio>; + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; }; };
Initialize audio PLL1 as the parent clock for 8kHz series rates, audio PLL2 as the parent clock for 11kHz series rates. that PLL1 and PLL2 can together support full range of audio sample rates. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 3 +++ 1 file changed, 3 insertions(+)