From patchwork Tue Mar 19 16:29:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13596894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 791F0C54E71 for ; Tue, 19 Mar 2024 16:29:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gc63iL5Qacx6XZlNH2yc+i61Jd/rY+1ZA0e3EN0FheM=; b=s3auDDRZGwPkJq PNQIosq2E9zjKqZrOIE3TpEuUR/D+md+BKkQ2WoZaXSXI2vrC1yyqhZXlgy96i0b1aLFTR+e5lvpG 1SR1ycGQDhoPd5c6WxrpvpnHuPzRxKSnKi7JO8/Dd3Jq54gLYAu42IsBEWgsK2BKIC3Z+J9tfC+JJ kJEEGENir4IjEgRbPfk1XxSVOKaeNmsi7sUji6eJFQNf5yDaX+UIu8sQEUPTGhajkyOn5phpzfyER D7x6Z4V3RGL/8/zYDm/tufHfwWymzSljuVSzkQyRd/iIckrHmReTmH/mR5KFUrguBzbNhkhLr9cIT yfnJMPP6ZAziZdgOlDgg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rmcL6-0000000DONg-3GtG; Tue, 19 Mar 2024 16:29:24 +0000 Received: from xavier.telenet-ops.be ([2a02:1800:120:4::f00:14]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rmcKz-0000000DOHO-0LVz for linux-arm-kernel@lists.infradead.org; Tue, 19 Mar 2024 16:29:18 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:76d0:2bff:fec8:549]) by xavier.telenet-ops.be with bizsmtp id 0gVA2C00S0SSLxL01gVAm9; Tue, 19 Mar 2024 17:29:11 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rmcKZ-0046H5-QX; Tue, 19 Mar 2024 17:29:10 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rmcKs-000pvS-MS; Tue, 19 Mar 2024 17:29:10 +0100 From: Geert Uytterhoeven To: Magnus Damm , =?utf-8?q?Niklas_S=C3=B6derlund?= Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 1/3] ARM: dts: renesas: r8a73a4: Add TMU nodes Date: Tue, 19 Mar 2024 17:29:05 +0100 Message-Id: <1a60832f3ba37afb4a5791f4e5db4610ab31beb3.1710864964.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240319_092917_298915_FEC90546 X-CRM114-Status: GOOD ( 11.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device nodes for the Timer Units (TMU) on the R-Mobile APE6 SoC, and the clocks serving them. Note that TMU channels 1 and 2 are not added, as their interrupts are not wired to the interrupt controller for the AP-System Core (INTC-SYS), only to the interrupt controller for the AP-Realtime Core (INTC-RT). Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund --- arch/arm/boot/dts/renesas/r8a73a4.dtsi | 37 +++++++++++++++++++++++ include/dt-bindings/clock/r8a73a4-clock.h | 4 +++ 2 files changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index ac654ff45d0e9a9c..9a2ae282a46ba4b1 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -60,6 +60,32 @@ timer { ; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a73a4", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&mstp1_clks R8A73A4_CLK_TMU0>; + clock-names = "fck"; + power-domains = <&pd_c5>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a73a4", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&mstp1_clks R8A73A4_CLK_TMU3>; + clock-names = "fck"; + power-domains = <&pd_a3r>; + status = "disabled"; + }; + dbsc1: memory-controller@e6790000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe6790000 0 0x10000>; @@ -654,6 +680,17 @@ extal1_div2_clk: extal1_div2 { }; /* Gate clocks */ + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&cp_clk>, <&mp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_TMU0 R8A73A4_CLK_TMU3 + >; + clock-output-names = + "tmu0", "tmu3"; + }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h index 1ec4827b80916054..655440a3e7c6868a 100644 --- a/include/dt-bindings/clock/r8a73a4-clock.h +++ b/include/dt-bindings/clock/r8a73a4-clock.h @@ -24,6 +24,10 @@ #define R8A73A4_CLK_ZS 14 #define R8A73A4_CLK_HP 15 +/* MSTP1 */ +#define R8A73A4_CLK_TMU0 25 +#define R8A73A4_CLK_TMU3 21 + /* MSTP2 */ #define R8A73A4_CLK_DMAC 18 #define R8A73A4_CLK_SCIFB3 17