From patchwork Mon Jan 6 14:36:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 3438601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 39072C02DC for ; Mon, 6 Jan 2014 14:41:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 893052016D for ; Mon, 6 Jan 2014 14:41:06 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8F18F20172 for ; Mon, 6 Jan 2014 14:40:59 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W0BKZ-0006P1-32; Mon, 06 Jan 2014 14:39:04 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W0BJy-0003lX-0u; Mon, 06 Jan 2014 14:38:26 +0000 Received: from mail-ee0-f45.google.com ([74.125.83.45]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W0BJe-0003gR-MW for linux-arm-kernel@lists.infradead.org; Mon, 06 Jan 2014 14:38:08 +0000 Received: by mail-ee0-f45.google.com with SMTP id d49so7922409eek.4 for ; Mon, 06 Jan 2014 06:37:45 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references:content-type; bh=Y5Waa11NVhpRmK3/qpnJt5r/XtuyYE4g20qxdFdl7Ro=; b=FoZtXsf5ijblpnRXBir7LdPAELh6pqEjAiRMS2AYvY6brRROqulNsnqS2jEbj4lV84 6wTq4Q4iUzTA3wChLXttHQ7tANEdpMKkQA91PpnvNyjvrXCmFEEjfJaxXrGgqpaJPpjg KtxYubMW15UUkapfW1iSD7eaRtwjh3ayw7Vp+dbmTgfQyW9FpvbytsazOOuNSXY1R70M 1pBqt5UFDh+aBZN4FLzX2C3bOO5e6J9xEvRrCAJa9l/5+Cf3EPQ0bCoUZDFbV92YOKTs fVuFxfBVXXjs345qeg3Hg5TK6KQL1tfwFXxgMp6kiH7k0YwaOVq3+rhsPpP5tBQWfNrS g4BQ== X-Gm-Message-State: ALoCoQlvGqLM2DR2aj6dpIkCLF+En2ACb8CoqMRv690jh4PhDqb1zByq31eVjir+UQU49vaaEWsd X-Received: by 10.15.22.137 with SMTP id f9mr35672404eeu.30.1389019064759; Mon, 06 Jan 2014 06:37:44 -0800 (PST) Received: from localhost (nat-63.starnet.cz. [178.255.168.63]) by mx.google.com with ESMTPSA id l4sm171467368een.13.2014.01.06.06.37.42 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 06 Jan 2014 06:37:43 -0800 (PST) From: Michal Simek To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Soren Brinkmann , Steffen Trumtrar Subject: [PATCH 6/7] ARM: zynq: Add and use zynq_slcr_read/write() helper functions Date: Mon, 6 Jan 2014 15:36:42 +0100 Message-Id: <1dc9cc7353d5999f46fd4bae9bdc9fbc56f0c274.1389018985.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140106_093806_905476_370FB62B X-CRM114-Status: GOOD ( 19.25 ) X-Spam-Score: -1.9 (-) Cc: Josh Cartwright , monstr@monstr.eu, Russell King , Peter Crosthwaite , linux-kernel@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_TVD_MIME_NO_HEADERS, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use zynq_slcr_read/write helper functions for reg access instead of readl/writel. Also use regmap when it is ready. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/slcr.c | 56 ++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 48 insertions(+), 8 deletions(-) -- 1.8.2.3 diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index a679dff..f0f6a69 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -35,6 +35,42 @@ static void __iomem *zynq_slcr_base; static struct regmap *zynq_slcr_regmap; /** + * zynq_slcr_write - Write to a register in SLCR block + * + * @val: Value to write to the register + * @offset: Register offset in SLCR block + * + * return: a negative value on error, 0 on success + */ +static int zynq_slcr_write(u32 val, u32 offset) +{ + if (!zynq_slcr_regmap) { + writel(val, zynq_slcr_base + offset); + return 0; + } + + return regmap_write(zynq_slcr_regmap, offset, val); +} + +/** + * zynq_slcr_read - Read a register in SLCR block + * + * @val: Pointer to value to be read from SLCR + * @offset: Register offset in SLCR block + * + * return: a negative value on error, 0 on success + */ +static int zynq_slcr_read(u32 *val, u32 offset) +{ + if (zynq_slcr_regmap) + return regmap_read(zynq_slcr_regmap, offset, val); + + *val = readl(zynq_slcr_base + offset); + + return 0; +} + +/** * zynq_slcr_system_reset - Reset the entire system. */ void zynq_slcr_system_reset(void) @@ -53,9 +89,9 @@ void zynq_slcr_system_reset(void) * the FSBL not loading the bitstream after soft-reboot * This is a temporary solution until we know more. */ - reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); - writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); - writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); + zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET); + zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET); + zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); } /** @@ -64,11 +100,13 @@ void zynq_slcr_system_reset(void) */ void zynq_slcr_cpu_start(int cpu) { - u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + u32 reg; + + zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); reg &= ~(SLCR_A9_CPU_RST << cpu); - writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); - writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); } /** @@ -77,9 +115,11 @@ void zynq_slcr_cpu_start(int cpu) */ void zynq_slcr_cpu_stop(int cpu) { - u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + u32 reg; + + zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; - writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); } /**