From patchwork Mon Jul 4 21:55:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell King - ARM Linux X-Patchwork-Id: 943012 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p64Lu0G4025445 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 4 Jul 2011 21:56:21 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qdr7E-0004RK-0W; Mon, 04 Jul 2011 21:55:40 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qdr7D-0003cv-K5; Mon, 04 Jul 2011 21:55:39 +0000 Received: from [2002:4e20:1eda::1] (helo=caramon.arm.linux.org.uk) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qdr75-0003cb-G2 for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2011 21:55:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=caramon; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=M0LFGrW4IaNqxVS8dGyOGOrbiuVLSPtYF+LDUST56r8=; b=GNSnUYkjGM6rv+Wcr7yTR15qnlIgsyv2VtxE2D3dOa5ffTBjipTc6ECjwgCFijRJlQ0TD9Bvdf+qoDRWMb7kJ76oslb9f6nitFqUuDUCc70kzLOZaYk5tKCWQT5D3xUnfzoZbTrfunxPQpZioeQw8BPkd3jDMBKXASftOeZfxwk=; Received: from n2100.arm.linux.org.uk ([2002:4e20:1eda:1:214:fdff:fe10:4f86]) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1Qdr6i-00029w-VP; Mon, 04 Jul 2011 22:55:09 +0100 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.72) (envelope-from ) id 1Qdr6h-0005Vt-DH; Mon, 04 Jul 2011 22:55:07 +0100 Date: Mon, 4 Jul 2011 22:55:07 +0100 From: Russell King - ARM Linux To: Catalin Marinas Subject: Re: Unnecessary cache-line flush on page table updates ? Message-ID: <20110704215507.GH8286@n2100.arm.linux.org.uk> References: <20110701101019.GA1723@e102109-lin.cambridge.arm.com> <20110704094531.GB19117@e102109-lin.cambridge.arm.com> <20110704100221.GB8286@n2100.arm.linux.org.uk> <20110704104329.GD19117@e102109-lin.cambridge.arm.com> <20110704111338.GD8286@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20110704111338.GD8286@n2100.arm.linux.org.uk> User-Agent: Mutt/1.5.19 (2009-01-05) X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110704_175536_486106_149E8C20 X-CRM114-Status: GOOD ( 23.70 ) X-Spam-Score: 1.4 (+) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (1.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 1.3 RDNS_NONE Delivered to internal network by a host with no rDNS 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid Cc: heechul Yun , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 04 Jul 2011 21:56:21 +0000 (UTC) On Mon, Jul 04, 2011 at 12:13:38PM +0100, Russell King - ARM Linux wrote: > As far as the BTB goes, I wonder if we can postpone that for user TLB > ops by setting a TIF_ flag and checking that before returning to userspace. > That would avoid having to needlessly destroy the cached branch information > for kernel space while looping over the page tables. The only other place > that needs to worry about that is module_alloc() and vmap/vmalloc with > PROT_KERNEL_EXEC, all of which can be done in flush_cache_vmap(). Actually, we don't need to do BTC invalidate in flush_cache_vmap(), but we do need to do a dsb+isb. Firstly, the majority of mappings are created with NX set, so the BTC can't be involved in anything created there (as we can't execute code there.) Secondly, if we're loading a code into kernel space to execute, then we need to ensure I/D coherency via flush_icache_range(), which has to happen after the mappings have been created, and this already does our BTC invalidate+dsb+isb. So, as far as kernel space TLB invalidation goes, my conclusion is that we do not have to touch the BTC at all there, and we can leave that to flush_icache_range() (and therefore cpu..coherent_kern_range) to deal with. Practically, testing it out on Versatile Express loading/unloading a few modules shows no ill effects from dropping the BTC invalidates from the kernel TLB invalidate ops. 8<---------- From: Russell King ARM: btc: avoid invalidating the branch target cache on kernel TLB maintanence Kernel space needs very little in the way of BTC maintanence as most mappings which are created and destroyed are non-executable, and so could never enter the instruction stream. The case which does warrant BTC maintanence is when a module is loaded. This creates a new executable mapping, but at that point the pages have not been initialized with code and data, so at that point they contain unpredictable information. Invalidating the BTC at this stage serves little useful purpose. Before we execute module code, we call flush_icache_range(), which deals with the BTC maintanence requirements. This ensures that we have a BTC maintanence operation before we execute code via the newly created mapping. Signed-off-by: Russell King --- arch/arm/include/asm/tlbflush.h | 23 ----------------------- arch/arm/mm/tlb-v6.S | 1 - arch/arm/mm/tlb-v7.S | 4 ---- 3 files changed, 0 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 9aeddce..3704d03 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -481,19 +481,6 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); if (tlb_flag(TLB_V7_UIS_PAGE)) asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc"); - - if (tlb_flag(TLB_BTB)) { - /* flush the branch target cache */ - asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); - dsb(); - isb(); - } - if (tlb_flag(TLB_V7_IS_BTB)) { - /* flush the branch target cache */ - asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc"); - dsb(); - isb(); - } } /* diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S index 73d7d89..cdbfda5 100644 --- a/arch/arm/mm/tlb-v6.S +++ b/arch/arm/mm/tlb-v6.S @@ -83,7 +83,6 @@ ENTRY(v6wbi_flush_kern_tlb_range) add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b - mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier mcr p15, 0, r2, c7, c5, 4 @ prefetch flush mov pc, lr diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S index 53cd5b4..dc84f72 100644 --- a/arch/arm/mm/tlb-v7.S +++ b/arch/arm/mm/tlb-v7.S @@ -75,11 +75,7 @@ ENTRY(v7wbi_flush_kern_tlb_range) add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b - mov r2, #0 - ALT_SMP(mcr p15, 0, r2, c7, c1, 6) @ flush BTAC/BTB Inner Shareable - ALT_UP(mcr p15, 0, r2, c7, c5, 6) @ flush BTAC/BTB dsb - isb mov pc, lr ENDPROC(v7wbi_flush_kern_tlb_range)