From patchwork Wed Jul 6 14:08:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Vorontsov X-Patchwork-Id: 949782 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p66E90So006415 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 6 Jul 2011 14:09:21 GMT Received: from canuck.infradead.org ([134.117.69.58]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QeSmR-0004Tf-Te; Wed, 06 Jul 2011 14:08:44 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QeSmR-0006LJ-J5; Wed, 06 Jul 2011 14:08:43 +0000 Received: from mail-fx0-f43.google.com ([209.85.161.43]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QeSmN-0006L0-P2 for linux-arm-kernel@lists.infradead.org; Wed, 06 Jul 2011 14:08:41 +0000 Received: by fxg17 with SMTP id 17so109689fxg.16 for ; Wed, 06 Jul 2011 07:08:35 -0700 (PDT) Received: by 10.223.83.137 with SMTP id f9mr10649007fal.18.1309961315385; Wed, 06 Jul 2011 07:08:35 -0700 (PDT) Received: from localhost (mail.dev.rtsoft.ru [213.79.90.226]) by mx.google.com with ESMTPS id o23sm6045848faa.9.2011.07.06.07.08.33 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jul 2011 07:08:34 -0700 (PDT) Date: Wed, 6 Jul 2011 18:08:32 +0400 From: Anton Vorontsov To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: cns3xxx: Add support for L2 Cache Controller Message-ID: <20110706140832.GA15946@oksana.dev.rtsoft.ru> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110706_100840_097223_AD7248D2 X-CRM114-Status: GOOD ( 18.15 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.161.43 listed in list.dnswl.org] Cc: Tommy Lin , Russell King , mac.lin@caviumnetworks.com, Arnd Bergmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 06 Jul 2011 14:09:21 +0000 (UTC) CNS3xxx SOCs have L310-compatible cache controller, so let's use it. With this patch benchmarking with 'gzip' shows that performance is doubled, and I'm still able to boot full-fledged userland over NFS (using PCIe NIC), so the support should be pretty robust. Signed-off-by: Anton Vorontsov --- I'm going to apply it to linux-cns3xxx.git tree and push it (via Arnd) for v3.1 , if there will be no complains, of course. Thanks, arch/arm/mach-cns3xxx/cns3420vb.c | 2 + arch/arm/mach-cns3xxx/core.c | 39 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-cns3xxx/core.h | 1 + arch/arm/mm/Kconfig | 2 +- 4 files changed, 43 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index 08e5c87..4b804ba 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -170,6 +170,8 @@ static struct platform_device *cns3420_pdevs[] __initdata = { static void __init cns3420_init(void) { + cns3xxx_l2x0_init(); + platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); cns3xxx_ahci_init(); diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index da30078..49f3a51 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "core.h" @@ -244,3 +245,41 @@ static void __init cns3xxx_timer_init(void) struct sys_timer cns3xxx_timer = { .init = cns3xxx_timer_init, }; + +void __init cns3xxx_l2x0_init(void) +{ + void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); + u32 val; + + if (WARN_ON(!base)) + return; + + /* + * Tag RAM Control register + * + * bit[10:8] - 1 cycle of write accesses latency + * bit[6:4] - 1 cycle of read accesses latency + * bit[3:0] - 1 cycle of setup latency + * + * 1 cycle of latency for setup, read and write accesses + */ + val = readl(base + L2X0_TAG_LATENCY_CTRL); + val &= 0xfffff888; + writel(val, base + L2X0_TAG_LATENCY_CTRL); + + /* + * Data RAM Control register + * + * bit[10:8] - 1 cycles of write accesses latency + * bit[6:4] - 1 cycles of read accesses latency + * bit[3:0] - 1 cycle of setup latency + * + * 1 cycle of setup latency, 2 cycles of read and write accesses latency + */ + val = readl(base + L2X0_DATA_LATENCY_CTRL); + val &= 0xfffff888; + writel(val, base + L2X0_DATA_LATENCY_CTRL); + + /* 32 KiB, 8-way, parity disable */ + l2x0_init(base, 0x00540000, 0xfe000fff); +} diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h index ffeb3a8..13635ca 100644 --- a/arch/arm/mach-cns3xxx/core.h +++ b/arch/arm/mach-cns3xxx/core.h @@ -14,6 +14,7 @@ extern struct sys_timer cns3xxx_timer; void __init cns3xxx_map_io(void); +void __init cns3xxx_l2x0_init(void); void __init cns3xxx_init_irq(void); void cns3xxx_power_off(void); diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 0074b8d..cb26d49 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -821,7 +821,7 @@ config CACHE_L2X0 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \ ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \ - ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE + ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_CNS3XXX default y select OUTER_CACHE select OUTER_CACHE_SYNC