From patchwork Mon Jul 11 16:49:20 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 965562 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p6BGnxdR008102 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 11 Jul 2011 16:50:20 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QgJg5-0000AP-FP; Mon, 11 Jul 2011 16:49:49 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QgJg5-0000iw-3f; Mon, 11 Jul 2011 16:49:49 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QgJg0-0000iJ-W6 for linux-arm-kernel@lists.infradead.org; Mon, 11 Jul 2011 16:49:46 +0000 Received: from e102109-lin.cambridge.arm.com (e102109-lin.cambridge.arm.com [10.1.77.45]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id p6BGkBY3016373; Mon, 11 Jul 2011 17:46:11 +0100 (BST) Date: Mon, 11 Jul 2011 17:49:20 +0100 From: Catalin Marinas To: Russell King - ARM Linux Subject: Re: Unnecessary cache-line flush on page table updates ? Message-ID: <20110711164919.GB18871@e102109-lin.cambridge.arm.com> References: <20110704094531.GB19117@e102109-lin.cambridge.arm.com> <20110704100221.GB8286@n2100.arm.linux.org.uk> <20110704104329.GD19117@e102109-lin.cambridge.arm.com> <20110704111338.GD8286@n2100.arm.linux.org.uk> <20110704155835.GA30189@e102109-lin.cambridge.arm.com> <20110704195819.GG8286@n2100.arm.linux.org.uk> <20110704232019.GK8286@n2100.arm.linux.org.uk> <20110706160551.GH32020@e102109-lin.cambridge.arm.com> <20110706180814.GL8286@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20110706180814.GL8286@n2100.arm.linux.org.uk> User-Agent: Mutt/1.5.20 (2009-06-14) X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110711_124945_293695_120C5CFB X-CRM114-Status: GOOD ( 22.30 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: heechul Yun , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Mon, 11 Jul 2011 16:50:20 +0000 (UTC) On Wed, Jul 06, 2011 at 07:08:14PM +0100, Russell King - ARM Linux wrote: > Okay, so I can say with confidence then that how things stand in my tree, > which limits BTC invalidation to: > > 1. For kernel mappings, flush_icache_range() which must be called prior > to code placed in them being executed. > > 2. For user mappings, __sync_icache_dcache's icache flush, which is > called before a non-zero user PTE is inserted. What about: flush_cache_user_range() flush_ptrace_access() They are fine as long as you haven't removed the BTC invalidation from __cpuc_coherent_(kern|user)_range. > The area which needs more to focus some further work is > __sync_icache_dcache(), which is fairly over-zealous about all the > flushing. Another thing that could be optimised is not to clean and invalidate the D-cache but only clean to the PoU. The only problem is that (flush|invalidate)_kernel_vmap_area, functions that seem to used only in a single place. The semantics in cachetlb.txt claim to be used for I/O, which means that they are already broken since we don't handle the L2 cache. 8<---------------------- From e7ad36d5866a93fb182e8edfc8ae03b5911cc3e6 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 11 Jul 2011 17:38:57 +0100 Subject: [PATCH 1/1] ARM: Only clean the D-cache to the PoU in v7_flush_kern_dcache_area() With PIPT caches (like ARMv7), there is no need to clean&invalidate the D-cache via the __cpuc_flush_dcache_area() function as there are no aliases. The D-cache only needs to be cleaned for the coherency with the I-cache. Signed-off-by: Catalin Marinas --- arch/arm/mm/cache-v7.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index d32f02b..b4faccd 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -224,7 +224,7 @@ ENTRY(v7_flush_kern_dcache_area) sub r3, r2, #1 bic r0, r0, r3 1: - mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line + mcr p15, 0, r0, c7, c11, 1 @ clean D line to the point of unification add r0, r0, r2 cmp r0, r1 blo 1b