From patchwork Wed Aug 10 10:31:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 1052602 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7AAWBEf017785 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 10 Aug 2011 10:32:32 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qr64p-0004eG-On; Wed, 10 Aug 2011 10:31:56 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qr64o-0003Ku-JC; Wed, 10 Aug 2011 10:31:54 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qr64l-0003JM-CL for linux-arm-kernel@lists.infradead.org; Wed, 10 Aug 2011 10:31:52 +0000 Received: from e102109-lin.cambridge.arm.com (e102109-lin.cambridge.arm.com [10.1.77.70]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id p7AAV711013402; Wed, 10 Aug 2011 11:31:07 +0100 (BST) Date: Wed, 10 Aug 2011 11:31:39 +0100 From: Catalin Marinas To: Siarhei Siamashka Subject: Re: [PATCH] ARM errata: Possible cache data corruption with hit-under-miss enabled Message-ID: <20110810103139.GD7464@e102109-lin.cambridge.arm.com> References: <1312785148-32531-1-git-send-email-siarhei.siamashka@gmail.com> <20110808100233.GG29226@e102109-lin.cambridge.arm.com> <20110808132631.GA670@e102109-lin.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110810_063151_698812_60D8E16D X-CRM114-Status: GOOD ( 27.99 ) X-Spam-Score: -3.1 (---) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-3.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [217.140.96.50 listed in list.dnswl.org] -0.8 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Wed, 10 Aug 2011 10:32:32 +0000 (UTC) X-MIME-Autoconverted: from quoted-printable to 8bit by demeter2.kernel.org id p7AAWBEf017785 On Tue, Aug 09, 2011 at 11:06:55PM +0100, Siarhei Siamashka wrote: > On Mon, Aug 8, 2011 at 4:26 PM, Catalin Marinas wrote: > > On Mon, Aug 08, 2011 at 12:43:00PM +0100, Siarhei Siamashka wrote: > >> On Mon, Aug 8, 2011 at 1:02 PM, Catalin Marinas wrote: > >> > On Mon, Aug 08, 2011 at 07:32:28AM +0100, Siarhei Siamashka wrote: > >> >> From: Catalin Marinas > >> >> > >> >> This patch is a workaround for the 364296 ARM1136 r0pX erratum (possible > >> >> cache data corruption with hit-under-miss enabled). It sets the > >> >> undocumented bit 31 in the auxiliary control register and the FI bit in > >> >> the control register, thus disabling hit-under-miss without putting the > >> >> processor into full low interrupt latency mode. > >> >> > >> >> Signed-off-by: Catalin Marinas > >> >> Tested-by: Siarhei Siamashka > >> > > >> > I haven't pushed this workaround in the past as I wasn't sure there is > >> > production hardware affected. I recall you mentioned Nokia N800, do you > >> > know which CPU revision does this have? > >> > >> [    0.000000] CPU: ARMv6-compatible processor [4107b362] revision 2 > >> (ARMv6TEJ), cr=00e5387f > >> [    0.000000] CPU: VIPT aliasing data cache, unknown instruction > >> cache > >> [    0.000000] Machine: Nokia N810 > >> [    0.000000] Memory policy: ECC disabled, Data cache writeback > >> [    0.000000] OMAP2420 > >> > >> # cat /proc/cpuinfo > >> Processor       : ARMv6-compatible processor rev 2 (v6l) > >> BogoMIPS        : 213.72 > >> Features        : swp half thumb fastmult vfp edsp java > >> CPU implementer : 0x41 > >> CPU architecture: 6TEJ > >> CPU variant     : 0x0 > >> CPU part        : 0xb36 > >> CPU revision    : 2 > >> > >> Hardware        : Nokia N810 > >> Revision        : 0000 > >> Serial          : 0000000000000000 > > ... > >> Would you be so kind to update the patch? > > > > OK, I'll update it and post the patch in the next day or so. > > Thanks a lot. I'll be sure to test it and respond to confirm that it > works fine (or not). See below. Thanks. 8<------------------------ From 0bbbd0ddc4e9e55998f4137c5f276c5997d8ef90 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Wed, 10 Aug 2011 11:26:46 +0100 Subject: [PATCH 1/1] ARM errata: Possible cache data corruption with hit-under-miss enabled This patch is a workaround for the 364296 ARM1136 r0p2 erratum (possible cache data corruption with hit-under-miss enabled). It sets the undocumented bit 31 in the auxiliary control register and the FI bit in the control register, thus disabling hit-under-miss without putting the processor into full low interrupt latency mode. Signed-off-by: Catalin Marinas Tested-by: Siarhei Siamashka --- arch/arm/Kconfig | 12 ++++++++++++ arch/arm/mm/proc-v6.S | 16 ++++++++++++++++ 2 files changed, 28 insertions(+), 0 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2c71a8f..30335e1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1272,6 +1272,18 @@ config ARM_ERRATA_754327 This workaround defines cpu_relax() as smp_mb(), preventing correctly written polling loops from denying visibility of updates to memory. +config ARM_ERRATA_364296 + bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" + depends on CPU_V6 && !SMP + help + This options enables the workaround for the 364296 ARM1136 + r0p2 erratum (possible cache data corruption with + hit-under-miss enabled). It sets the undocumented bit 31 in + the auxiliary control register and the FI bit in the control + register, thus disabling hit-under-miss without putting the + processor into full low interrupt latency mode. ARM11MPCore + is not affected. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 219138d..a923aa0 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -223,6 +223,22 @@ __v6_setup: mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them +#ifdef CONFIG_ARM_ERRATA_364296 + /* + * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data + * corruption with hit-under-miss enabled). The conditional code below + * (setting the undocumented bit 31 in the auxiliary control register + * and the FI bit in the control register) disables hit-under-miss + * without putting the processor into full low interrupt latency mode. + */ + ldr r6, =0x4107b362 @ id for ARM1136 r0p2 + mrc p15, 0, r5, c0, c0, 0 @ get processor id + teq r5, r6 @ check for the faulty core + mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg + orreq r5, r5, #(1 << 31) @ set the undocumented bit 31 + mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg + orreq r0, r0, #(1 << 21) @ low interrupt latency configuration +#endif mov pc, lr @ return to head.S:__ret /*