@@ -85,6 +85,20 @@
phy-mode = "gmii";
};
+ rtc0: rtc@00000 {
+ compatible = "not-there-picochip,pc3x2-rtc";
+ clock-freq = <200000000>;
+ reg = <0x00000 0xf>;
+ interrupts = <8>;
+ };
+
+ timer0: timer@ffd00000 {
+ compatible = "picochip,pc3x2-timer";
+ interrupts = <169>;
+ clock-freq = <200000000>;
+ reg = <0xffd00000 0x14>;
+ interrupt-parent = <&intc>;
+ };
};
};
};
@@ -106,14 +106,15 @@ static void __init picoxcell_timer_init(void)
panic("No timer for clockevent");
picoxcell_add_clockevent(event_timer);
+#if 0
source_timer = of_find_matching_node(event_timer, picoxcell_timer_ids);
if (!source_timer)
panic("No timer for clocksource");
picoxcell_add_clocksource(source_timer);
-
+#endif
of_node_put(source_timer);
- picoxcell_init_sched_clock();
+// picoxcell_init_sched_clock();
}
struct sys_timer picoxcell_timer = {
@@ -4,6 +4,7 @@ config MACH_SOCFPGA_CYCLONE5
select HAVE_SMP
select PLAT_SOCFPGA_ETH
select COMMON_CLK
+ select DW_APB_TIMER
help
Include support for the Altera(R) Cyclone5 development platform.
@@ -42,6 +42,8 @@
#include "common.h"
+#include "../../../arch/arm/mach-picoxcell/time.c"
+
extern struct dw_mci_board sdmmc_platform_data;
extern struct dma_pl330_platdata dma_platform_data;
@@ -112,6 +114,15 @@ void __init socfpga_timer_init(void __iomem *src_timer_base,
writel(0, osc_timer0_va_base + TIMER_CTRL);
writel(0, osc_timer1_va_base + TIMER_CTRL);
+#if 0
+ /* Fall back to jiffies? */
dwapbt_clocksource_init(src_timer_base);
+#endif
+
+#if 0
+ /* Use dt-based code from picoxcell */
dwapbt_clockevents_init(event_timer_base, event_timer_irq);
+#endif
+
+ picoxcell_timer_init();
}
@@ -118,6 +118,7 @@ static void __init socfpga_cyclone5_timer_init(void)
socfpga_timer_init(sp_timer0_va_base, osc_timer0_va_base,
IRQ_SOCFPGA_L4_OSC1_TIMER0);
+
#ifdef CONFIG_OF
twd_local_timer_of_register();
#endif