From patchwork Thu Aug 9 10:24:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot for Dave Martin X-Patchwork-Id: 1299771 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 3340B3FC23 for ; Thu, 9 Aug 2012 10:27:25 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SzPum-00087f-Lw; Thu, 09 Aug 2012 10:24:29 +0000 Received: from mail-ey0-f177.google.com ([209.85.215.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SzPui-00086P-Ly for linux-arm-kernel@lists.infradead.org; Thu, 09 Aug 2012 10:24:25 +0000 Received: by eaai12 with SMTP id i12so81614eaa.36 for ; Thu, 09 Aug 2012 03:24:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=yLxC90cyouEv0XDmnwVqpggOoUwJ+6g+PYovuH4gVkA=; b=UHoGxeYyXLTyyDkO7DgoJephS6A7LwpfQgW6nTmGqg133JSDH1OWVdAy7tZTojOolv n9/QOfGdHZ1iJJTUpPkUYjVfy3nN3ZZo6Xwe5vyyupnwKks2ysREmyH4pgHqsU0PEzLt 5LaBxQ5AsEZTyFM8fVFCfE/utg9kq31/EwF6G1E6whumFRm9GsTczeC9zB5W0JcKx67d lEeYBQsU8YAv6NrQ1WrXmxV2dOUPn4/5AUneEBudzb/3chS0WgFZc252vHGrnoImY2gA LLe7QA/jHw4eQKrc4H4MgLP7PzqmUgur2oxr6GXPVd1naU/UGLpDujWBFoxOvfRPEZPM 6w9w== Received: by 10.14.178.67 with SMTP id e43mr26790780eem.44.1344507862282; Thu, 09 Aug 2012 03:24:22 -0700 (PDT) Received: from linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id j4sm2253586eeo.11.2012.08.09.03.24.20 (version=SSLv3 cipher=OTHER); Thu, 09 Aug 2012 03:24:21 -0700 (PDT) Date: Thu, 9 Aug 2012 11:24:14 +0100 From: Dave Martin To: Matt Sealey Subject: Re: [PATCH 1/2] ARM: build ssi-fiq.S in ARM mode to prevent CONFIG_THUMB2_KERNEL build breakage Message-ID: <20120809102414.GA17588@linaro.org> References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com> <1344379514-30076-2-git-send-email-matt@genesi-usa.com> <20120808065502.GI1451@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQkfrczOkoNP+LyckvY7K/6LzWRcs0TqCbyshDmax6hCL/0tcc3jq5GamgUqF/m3p0DmgP9E X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Steev Klimaszewski , Sascha Hauer , Mark Brown , Linux Kernel Mailing List , Anton Vorontsov , Sascha Hauer , Shawn Guo , Linux ARM Kernel Mailing List X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Wed, Aug 08, 2012 at 12:32:39PM -0500, Matt Sealey wrote: [...] > I'm going to do a trapse through and find where Russell nacked Dave's > thumb-aware > rewrite.. would you mind if you have any of these boards seeing if it > really DOES There was no NAK because I didn't get as far as posting the patch, mostly because of the doubt about whether this code is ever relevant on Thumb2-capable hardware. If somebody with some old imx hardware that definitely relies on this wants to pick it up and test it, it might still be useful. I don't know whether I still have the original patch, but I think the only think I did was to swap the roles of r13 and r12. In the original code r12 is only used as a base register, which is permissible usage for r13 in Thumb-2. Those two registers appear private to the fiq handler, so I don't think the change will break anything, but I'd be more confident is somebody is able to test it. Cheers ---Dave diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S index 8397a2d..3589afb 100644 --- a/arch/arm/plat-mxc/ssi-fiq.S +++ b/arch/arm/plat-mxc/ssi-fiq.S @@ -35,19 +35,19 @@ .global imx_ssi_fiq_tx_buffer imx_ssi_fiq_start: - ldr r12, imx_ssi_fiq_base + ldr r13, imx_ssi_fiq_base /* TX */ ldr r11, imx_ssi_fiq_tx_buffer /* shall we send? */ - ldr r13, [r12, #SSI_SIER] - tst r13, #SSI_SIER_TFE0_EN + ldr r12, [r13, #SSI_SIER] + tst r12, #SSI_SIER_TFE0_EN beq 1f /* TX FIFO empty? */ - ldr r13, [r12, #SSI_SISR] - tst r13, #SSI_SISR_TFE0 + ldr r12, [r13, #SSI_SISR] + tst r12, #SSI_SISR_TFE0 beq 1f mov r10, #0x10000 @@ -56,34 +56,34 @@ imx_ssi_fiq_start: add r11, r11, r10 - ldrh r13, [r11] - strh r13, [r12, #SSI_STX0] + ldrh r12, [r11] + strh r12, [r13, #SSI_STX0] - ldrh r13, [r11, #2] - strh r13, [r12, #SSI_STX0] + ldrh r12, [r11, #2] + strh r12, [r13, #SSI_STX0] - ldrh r13, [r11, #4] - strh r13, [r12, #SSI_STX0] + ldrh r12, [r11, #4] + strh r12, [r13, #SSI_STX0] - ldrh r13, [r11, #6] - strh r13, [r12, #SSI_STX0] + ldrh r12, [r11, #6] + strh r12, [r13, #SSI_STX0] add r10, #8 - lsr r13, r8, #16 /* r13: buffer size */ - cmp r10, r13 - lslgt r8, r13, #16 + lsr r12, r8, #16 /* r12: buffer size */ + cmp r10, r12 + lslgt r8, r12, #16 addle r8, #8 1: /* RX */ /* shall we receive? */ - ldr r13, [r12, #SSI_SIER] - tst r13, #SSI_SIER_RFF0_EN + ldr r12, [r13, #SSI_SIER] + tst r12, #SSI_SIER_RFF0_EN beq 1f /* RX FIFO full? */ - ldr r13, [r12, #SSI_SISR] - tst r13, #SSI_SISR_RFF0 + ldr r12, [r13, #SSI_SISR] + tst r12, #SSI_SISR_RFF0 beq 1f ldr r11, imx_ssi_fiq_rx_buffer @@ -94,31 +94,31 @@ imx_ssi_fiq_start: add r11, r11, r10 - ldr r13, [r12, #SSI_SACNT] - tst r13, #SSI_SACNT_AC97EN + ldr r12, [r13, #SSI_SACNT] + tst r12, #SSI_SACNT_AC97EN - ldr r13, [r12, #SSI_SRX0] - strh r13, [r11] + ldr r12, [r13, #SSI_SRX0] + strh r12, [r11] - ldr r13, [r12, #SSI_SRX0] - strh r13, [r11, #2] + ldr r12, [r13, #SSI_SRX0] + strh r12, [r11, #2] /* dummy read to skip slot 12 */ - ldrne r13, [r12, #SSI_SRX0] + ldrne r12, [r13, #SSI_SRX0] - ldr r13, [r12, #SSI_SRX0] - strh r13, [r11, #4] + ldr r12, [r13, #SSI_SRX0] + strh r12, [r11, #4] - ldr r13, [r12, #SSI_SRX0] - strh r13, [r11, #6] + ldr r12, [r13, #SSI_SRX0] + strh r12, [r11, #6] /* dummy read to skip slot 12 */ - ldrne r13, [r12, #SSI_SRX0] + ldrne r12, [r13, #SSI_SRX0] add r10, #8 - lsr r13, r9, #16 /* r13: buffer size */ - cmp r10, r13 - lslgt r9, r13, #16 + lsr r12, r9, #16 /* r12: buffer size */ + cmp r10, r12 + lslgt r9, r12, #16 addle r9, #8 1: