From patchwork Thu Sep 13 01:00:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 1449851 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (unknown [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 702303FCFC for ; Thu, 13 Sep 2012 01:27:33 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TBxo2-0003ML-Q7; Thu, 13 Sep 2012 01:01:22 +0000 Received: from kirsty.vergenet.net ([202.4.237.240]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TBxny-0003LD-Lq for linux-arm-kernel@lists.infradead.org; Thu, 13 Sep 2012 01:01:19 +0000 Received: from ayumi.akashicho.tokyo.vergenet.net (p6117-ipbfp1901kobeminato.hyogo.ocn.ne.jp [114.172.117.117]) by kirsty.vergenet.net (Postfix) with ESMTP id D190D25BF1A; Thu, 13 Sep 2012 11:00:45 +1000 (EST) Received: by ayumi.akashicho.tokyo.vergenet.net (Postfix, from userid 7100) id 1EB2EEDE60F; Thu, 13 Sep 2012 10:00:42 +0900 (JST) Date: Thu, 13 Sep 2012 10:00:42 +0900 From: Simon Horman To: Stephen Boyd Subject: Re: [PATCH 2/2] arm: Add ARM ERRATA 782773 workaround Message-ID: <20120913010041.GD7622@verge.net.au> References: <1347434097-7924-1-git-send-email-horms@verge.net.au> <1347434097-7924-3-git-send-email-horms@verge.net.au> <5050CD87.4020800@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <5050CD87.4020800@codeaurora.org> Organisation: Horms Solutions Ltd. User-Agent: Mutt/1.5.21 (2010-09-15) X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [202.4.237.240 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Paul Mundt , Magnus Damm , linux-arm-kernel@lists.infradead.org, Russell King , linux-sh@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Wed, Sep 12, 2012 at 10:59:35AM -0700, Stephen Boyd wrote: > On 09/12/12 00:14, Simon Horman wrote: > > @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420 > > deadlock. This workaround puts DSB before executing ISB at the > > beginning of the abort exception handler. > > > > +config ARM_ERRATA_782773 > > + bool "ARM errata: Updating a translation entry might cause an unexpected translation fault" > > + depends on CPU_V7 > > + help > > + This option enables the workaround for the 782773 Cortex-A9 (all r0, > > + ,r2 and r3 revisions) erratum. It might cause MMU exception in case > > Seems to be an extra comma here. Thanks, here is an updated version. From: Kouei Abe arm: Add ARM ERRATA 782773 workaround Signed-off-by: Kouei Abe Signed-off-by: Simon Horman --- arch/arm/Kconfig | 9 +++++++++ arch/arm/mm/proc-v7-2level.S | 8 ++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 74fbdf7..6367fd9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420 deadlock. This workaround puts DSB before executing ISB at the beginning of the abort exception handler. +config ARM_ERRATA_782773 + bool "ARM errata: Updating a translation entry might cause an unexpected translation fault" + depends on CPU_V7 + help + This option enables the workaround for the 782773 Cortex-A9 (all r0, + r2 and r3 revisions) erratum. It might cause MMU exception in case + page table walk happens just after updating the existing + with setting page table in L1 data cache. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index fd045e7..9207b9f 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -103,9 +103,17 @@ ENTRY(cpu_v7_set_pte_ext) tstne r1, #L_PTE_PRESENT moveq r3, #0 +#ifdef CONFIG_ARM_ERRATA_782773 + mrs r2, cpsr @ save cpsr + cpsid if @ disable interrupts + mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line +#endif ARM( str r3, [r0, #2048]! ) THUMB( add r0, r0, #2048 ) THUMB( str r3, [r0] ) +#ifdef CONFIG_ARM_ERRATA_782773 + msr cpsr_c, r2 @ load cpsr +#endif mcr p15, 0, r0, c7, c10, 1 @ flush_pte #endif mov pc, lr