From patchwork Fri Sep 21 01:00:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 1488601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id DE4F5DF2D2 for ; Fri, 21 Sep 2012 01:02:40 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TErbo-0005tl-KW; Fri, 21 Sep 2012 01:00:44 +0000 Received: from kirsty.vergenet.net ([202.4.237.240]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TErbk-0005tX-Qq for linux-arm-kernel@lists.infradead.org; Fri, 21 Sep 2012 01:00:41 +0000 Received: from ayumi.akashicho.tokyo.vergenet.net (p6117-ipbfp1901kobeminato.hyogo.ocn.ne.jp [114.172.117.117]) by kirsty.vergenet.net (Postfix) with ESMTP id 5FFF425BE9C; Fri, 21 Sep 2012 11:00:39 +1000 (EST) Received: by ayumi.akashicho.tokyo.vergenet.net (Postfix, from userid 7100) id 03393EDE5B0; Fri, 21 Sep 2012 10:00:37 +0900 (JST) Date: Fri, 21 Sep 2012 10:00:37 +0900 From: Simon Horman To: Catalin Marinas Subject: Re: [PATCH 2/2] arm: Add ARM ERRATA 782773 workaround Message-ID: <20120921010037.GI21660@verge.net.au> References: <1347434097-7924-1-git-send-email-horms@verge.net.au> <1347434097-7924-3-git-send-email-horms@verge.net.au> <5050CD87.4020800@codeaurora.org> <20120913010041.GD7622@verge.net.au> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Organisation: Horms Solutions Ltd. User-Agent: Mutt/1.5.21 (2010-09-15) X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [202.4.237.240 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-sh@vger.kernel.org, Stephen Boyd , Magnus Damm , Paul Mundt , linux-arm-kernel@lists.infradead.org, Russell King X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Thu, Sep 20, 2012 at 10:35:50AM +0100, Catalin Marinas wrote: > On 13 September 2012 02:00, Simon Horman wrote: > > On Wed, Sep 12, 2012 at 10:59:35AM -0700, Stephen Boyd wrote: > >> On 09/12/12 00:14, Simon Horman wrote: > >> > @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420 > >> > deadlock. This workaround puts DSB before executing ISB at the > >> > beginning of the abort exception handler. > >> > > >> > +config ARM_ERRATA_782773 > >> > + bool "ARM errata: Updating a translation entry might cause an unexpected translation fault" > >> > + depends on CPU_V7 > >> > + help > >> > + This option enables the workaround for the 782773 Cortex-A9 (all r0, > >> > + ,r2 and r3 revisions) erratum. It might cause MMU exception in case > >> > >> Seems to be an extra comma here. > > > > Thanks, here is an updated version. > > > > From: Kouei Abe > > > > arm: Add ARM ERRATA 782773 workaround > > > > Signed-off-by: Kouei Abe > > Signed-off-by: Simon Horman > > I would add some text to the commit log as well, even though it > matches the Kconfig entry. Sure, an updated patch is below. I also reworded the text to make it easier on my eyes, I don't think the meaning has been altered. > Have you hit this in practice? In general the kernel shouldn't access > kernel virtual address corresponding to a page table that is being > changed. For user address space it is possible but the kernel can > handle use translation faults, even though they may be spurious. I believe that Abe-san's team have come up against this, I can confirm that if it is important. ---------------------------------------------------------------- From: Kouei Abe arm: Add ARM ERRATA 782773 workaround This is a workaround for Errata 782773 which effects all r0, r2 and r3 revisions. The work-around avoids the possibility of an MMU exception in the case where a page table walk occurs immediately after a page table update that hasn't been flushed from the L1 data cache. Cc: Catalin Marinas Signed-off-by: Kouei Abe Signed-off-by: Simon Horman --- v2 * Reword Kconfig description * Add some details to changelog entry diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 48c19d4..2b76164 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1423,6 +1423,15 @@ config ARM_ERRATA_775420 to deadlock. This workaround puts DSB before executing ISB if an abort may occur on cache maintenance. +config ARM_ERRATA_782773 + bool "ARM errata: Updating a translation entry might cause an unexpected translation fault" + depends on CPU_V7 + help + This option enables the workaround for the 782773 Cortex-A9 (all r0, + r2 and r3 revisions) erratum. It might cause MMU exception in case + page table walk happens just after updating the existing + with setting page table in L1 data cache. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index fd045e7..9207b9f 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -103,9 +103,17 @@ ENTRY(cpu_v7_set_pte_ext) tstne r1, #L_PTE_PRESENT moveq r3, #0 +#ifdef CONFIG_ARM_ERRATA_782773 + mrs r2, cpsr @ save cpsr + cpsid if @ disable interrupts + mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line +#endif ARM( str r3, [r0, #2048]! ) THUMB( add r0, r0, #2048 ) THUMB( str r3, [r0] ) +#ifdef CONFIG_ARM_ERRATA_782773 + msr cpsr_c, r2 @ load cpsr +#endif mcr p15, 0, r0, c7, c10, 1 @ flush_pte #endif mov pc, lr