From patchwork Mon Oct 22 06:49:18 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 1623861 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 3AE91400E8 for ; Mon, 22 Oct 2012 06:52:11 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TQBpT-0007zp-9k; Mon, 22 Oct 2012 06:49:39 +0000 Received: from mail-vb0-f49.google.com ([209.85.212.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TQBoz-0007vu-6H for linux-arm-kernel@lists.infradead.org; Mon, 22 Oct 2012 06:49:10 +0000 Received: by mail-vb0-f49.google.com with SMTP id fo1so2546201vbb.36 for ; Sun, 21 Oct 2012 23:49:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=ktV9CUwBlK4g1J2qboz/vKvN6VstEoKvTOkm+NU05Kw=; b=CnqgDDxs8xtGLS1BOHrJi4jYw+hshHgWYmYKpSsDaPhJmoZLnqIPnfU9H0BAtwKzMt ZykbZogoL4gGpyiMRn8NPcnlLt4jZL0rjem+/fYUR1B4zFEOpxkJIkYDzxleA1mTTU+c ZN8UPMc92FDAhW8KZPAaa8+gCjUINOq8N2SoBH5QFR9+464I1oJsZ1rbq0/wQj2dA48G bgaBZ5AolIV0MvaUfArePrJzvZIHFvEsNw9+4W0LFVFDvqGAnQmEh2KNtzVsvIYNcQE7 L2eE81CxDy9Kr6hDjsL5XnNjunZ1Swprk/Ii0ljzg18Mto0vxlrX5tWI3LN9bjFvy8wQ sVIw== Received: by 10.58.12.231 with SMTP id b7mr14315950vec.28.1350888548826; Sun, 21 Oct 2012 23:49:08 -0700 (PDT) Received: from [127.0.1.1] (pool-72-80-83-148.nycmny.fios.verizon.net. [72.80.83.148]) by mx.google.com with ESMTPS id dq8sm8966025vdc.4.2012.10.21.23.49.07 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 21 Oct 2012 23:49:08 -0700 (PDT) Subject: [PATCH v3 03/14] ARM: Factor out cpuid implementor and part number To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu From: Christoffer Dall Date: Mon, 22 Oct 2012 02:49:18 -0400 Message-ID: <20121022064918.18444.99781.stgit@ubuntu> In-Reply-To: <20121022064831.18444.73273.stgit@ubuntu> References: <20121022064831.18444.73273.stgit@ubuntu> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmqK9BprRyo+3E87UQNlTVEMhmObRAKjZr4NwV/MIXbqiKQed/rtv0Vz+DyUzTHwBtMkuvv X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Marcelo Tosatti X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Decoding the implementor and part number of the CPU id in the CPU ID register is needed by KVM, so we factor it out to share the code. Reviewed-by: Marcelo Tosatti Signed-off-by: Christoffer Dall --- arch/arm/include/asm/cputype.h | 26 ++++++++++++++++++++++++++ arch/arm/kernel/perf_event_cpu.c | 30 +++++++++++++++--------------- 2 files changed, 41 insertions(+), 15 deletions(-) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index cb47d28..306fb2c 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -51,6 +51,22 @@ extern unsigned int processor_id; #define read_cpuid_ext(reg) 0 #endif +#define IMPLEMENTOR_ARM 0x41 +#define IMPLEMENTOR_INTEL 0x69 + +#define PART_NUMBER_ARM1136 0xB360 +#define PART_NUMBER_ARM1156 0xB560 +#define PART_NUMBER_ARM1176 0xB760 +#define PART_NUMBER_ARM11MPCORE 0xB020 +#define PART_NUMBER_CORTEX_A8 0xC080 +#define PART_NUMBER_CORTEX_A9 0xC090 +#define PART_NUMBER_CORTEX_A5 0xC050 +#define PART_NUMBER_CORTEX_A15 0xC0F0 +#define PART_NUMBER_CORTEX_A7 0xC070 + +#define PART_NUMBER_XSCALE1 0x1 +#define PART_NUMBER_XSCALE2 0x2 + /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID @@ -61,6 +77,16 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } +static inline unsigned int __attribute_const__ read_cpuid_implementor(void) +{ + return (read_cpuid_id() & 0xFF000000) >> 24; +} + +static inline unsigned int __attribute_const__ read_cpuid_part_number(void) +{ + return (read_cpuid_id() & 0xFFF0); +} + static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) { return read_cpuid(CPUID_CACHETYPE); diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index 8d7d8d4..ff18566 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -200,46 +200,46 @@ static struct arm_pmu *__devinit probe_current_pmu(void) struct arm_pmu *pmu = NULL; int cpu = get_cpu(); unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); + unsigned long implementor = read_cpuid_implementor(); + unsigned long part_number = read_cpuid_part_number(); pr_info("probing PMU on CPU %d\n", cpu); /* ARM Ltd CPUs. */ - if (0x41 == implementor) { + if (implementor == IMPLEMENTOR_ARM) { switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ + case PART_NUMBER_ARM1136: + case PART_NUMBER_ARM1156: + case PART_NUMBER_ARM1176: pmu = armv6pmu_init(); break; - case 0xB020: /* ARM11mpcore */ + case PART_NUMBER_ARM11MPCORE: pmu = armv6mpcore_pmu_init(); break; - case 0xC080: /* Cortex-A8 */ + case PART_NUMBER_CORTEX_A8: pmu = armv7_a8_pmu_init(); break; - case 0xC090: /* Cortex-A9 */ + case PART_NUMBER_CORTEX_A9: pmu = armv7_a9_pmu_init(); break; - case 0xC050: /* Cortex-A5 */ + case PART_NUMBER_CORTEX_A5: pmu = armv7_a5_pmu_init(); break; - case 0xC0F0: /* Cortex-A15 */ + case PART_NUMBER_CORTEX_A15: pmu = armv7_a15_pmu_init(); break; - case 0xC070: /* Cortex-A7 */ + case PART_NUMBER_CORTEX_A7: pmu = armv7_a7_pmu_init(); break; } /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { + } else if (implementor == IMPLEMENTOR_INTEL) { part_number = (cpuid >> 13) & 0x7; switch (part_number) { - case 1: + case PART_NUMBER_XSCALE1: pmu = xscale1pmu_init(); break; - case 2: + case PART_NUMBER_XSCALE2: pmu = xscale2pmu_init(); break; }