From patchwork Wed Jan 9 11:46:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 1952291 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 233DDDF25A for ; Wed, 9 Jan 2013 11:50:51 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tsu7t-0001pS-9R; Wed, 09 Jan 2013 11:47:21 +0000 Received: from hqemgate04.nvidia.com ([216.228.121.35]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tsu7o-0001oR-H9 for linux-arm-kernel@lists.infradead.org; Wed, 09 Jan 2013 11:47:17 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Wed, 09 Jan 2013 03:46:55 -0800 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 09 Jan 2013 03:47:11 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 09 Jan 2013 03:47:11 -0800 Received: from deemhub02.nvidia.com (10.21.69.138) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.279.1; Wed, 9 Jan 2013 03:46:46 -0800 Received: from DEMAIL01.nvidia.com ([10.21.69.140]) by deemhub02.nvidia.com ([10.21.69.138]) with mapi; Wed, 9 Jan 2013 12:46:43 +0100 From: Hiroshi Doyu To: "lorenzo.pieralisi@arm.com" Date: Wed, 9 Jan 2013 12:46:41 +0100 Subject: Re: [v2 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU Thread-Topic: [v2 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU Thread-Index: Ac3uXv7Q7MMZu/9FSNy3vXc6GzxIIA== Message-ID: <20130109.134641.1582472136842052082.hdoyu@nvidia.com> References: <20130108.165342.1996373920678167735.hdoyu@nvidia.com><20130108162056.GA28618@e106331-lin.cambridge.arm.com><20130108171103.GA7417@e102568-lin.cambridge.arm.com> In-Reply-To: <20130108171103.GA7417@e102568-lin.cambridge.arm.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-nvconfidentiality: public acceptlanguage: en-US MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130109_064716_747085_31BC18E0 X-CRM114-Status: GOOD ( 24.12 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.35 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: "mark.rutland@arm.com" , "linux-tegra@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Hi Lorenzo, Lorenzo Pieralisi wrote @ Tue, 8 Jan 2013 18:11:03 +0100: > On Tue, Jan 08, 2013 at 04:21:38PM +0000, Mark Rutland wrote: > > On Tue, Jan 08, 2013 at 02:53:42PM +0000, Hiroshi Doyu wrote: > > [...] > > > > > > static void __init tegra_smp_init_cpus(void) > > > > > { > > > > > - unsigned int i, ncores = scu_get_core_count(scu_base); > > > > > + unsigned int i, cpu_id, ncores; > > > > > + u32 l2ctlr; > > > > > + phys_addr_t pa; > > > > > + > > > > > + cpu_id = read_cpuid(CPUID_ID) & CPU_MASK; > > > > > + switch (cpu_id) { > > > > > + case CPU_CORTEX_A15: > > > > > + asm("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); > > > > > + ncores = ((l2ctlr >> 24) & 3) + 1; > > > > > + break; > > > > > > > > [...] > > > > > > > > As mentioned last time [1], you should get this information from the dt > > > > instead. > > > > > > Most of platsmp.c:.smp_init_cpus() implementations seem just to > > > overwrite # of cores by SCU/MRC detection. Is there any implementation > > > to use the DT's # and skip SCU/MRC detection in .smp_init_cpus()? > > > > As far as I can see, there's no other platform which just relies on > > arm_dt_init_cpu_maps. Until recently, it didn't exist, so that makes some > > sense. As far as I can see, for the Tegra 114 you only need your smp_init_cpus > > to call set_smp_cross_call(gic_raise_softirq). Everything else you do seems to > > be handled by arm_dt_init_cpus. > > > > I think the best option would be to have a separate smp_ops for your dt > > platforms where we know cpu nodes are populated (e.g. Tegra 114), where > > smp_init_cpus is different to that for non-dt platforms. That way non dt > > platforms can keep the SCU hack for now, and won't be broken, and the dt > > platforms are far removed from the SCU hack and just use common infrastructure. > > > > Maybe someone else has a better idea? > > Have a look at mach-vexpress/platsmp.c (keeping in mind that the > GENERIC_SCU case will be refactored/removed since arm_dt_init_cpu_maps() is > doing most of the required steps), please let me know what you think. In tegra, we don't support non-DT. What about falling back SCU/MRC based detection only when arm_dt_init_cpu_maps() fails? diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 68e76ef..51d24ae 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -152,7 +152,7 @@ done: * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ -static void __init tegra_smp_init_cpus(void) +static void __init tegra_smp_detect_cores(void) { unsigned int i, cpu_id, ncores; u32 l2ctlr; @@ -183,6 +183,12 @@ static void __init tegra_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); +} + +static void __init tegra_smp_init_cpus(void) +{ + if (!num_possible_cpus()) + tegra_smp_detect_cores(); set_smp_cross_call(gic_raise_softirq); }