From patchwork Thu Jan 10 12:58:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 1960211 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 2AB8FDF264 for ; Thu, 10 Jan 2013 13:03:45 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TtHiE-0006Xc-59; Thu, 10 Jan 2013 12:58:26 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TtHi8-0006VD-E0 for linux-arm-kernel@lists.infradead.org; Thu, 10 Jan 2013 12:58:21 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Thu, 10 Jan 2013 05:02:18 -0800 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 10 Jan 2013 04:58:18 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 10 Jan 2013 04:58:18 -0800 Received: from deemhub01.nvidia.com (10.21.69.137) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.279.1; Thu, 10 Jan 2013 04:58:18 -0800 Received: from DEMAIL01.nvidia.com ([10.21.69.140]) by deemhub01.nvidia.com ([10.21.69.137]) with mapi; Thu, 10 Jan 2013 13:58:15 +0100 From: Hiroshi Doyu To: "lorenzo.pieralisi@arm.com" Date: Thu, 10 Jan 2013 13:58:13 +0100 Subject: Re: [v2 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU Thread-Topic: [v2 3/9] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU Thread-Index: Ac3vMic0+Wo9s6y0QBSV4Lp5TZ26xQ== Message-ID: <20130110.145813.1159140334089730421.hdoyu@nvidia.com> References: <20130108171103.GA7417@e102568-lin.cambridge.arm.com><20130109.134641.1582472136842052082.hdoyu@nvidia.com><20130109151700.GB22147@e102568-lin.cambridge.arm.com> In-Reply-To: <20130109151700.GB22147@e102568-lin.cambridge.arm.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-nvconfidentiality: public acceptlanguage: en-US MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130110_075820_878930_6C88EFAE X-CRM114-Status: GOOD ( 23.33 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: "Mark.Rutland@arm.com" , "linux-tegra@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Lorenzo Pieralisi wrote @ Wed, 9 Jan 2013 16:17:00 +0100: .... > > diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c > > index 68e76ef..51d24ae 100644 > > --- a/arch/arm/mach-tegra/platsmp.c > > +++ b/arch/arm/mach-tegra/platsmp.c > > @@ -152,7 +152,7 @@ done: > > * Initialise the CPU possible map early - this describes the CPUs > > * which may be present or become present in the system. > > */ > > -static void __init tegra_smp_init_cpus(void) > > +static void __init tegra_smp_detect_cores(void) > > { > > unsigned int i, cpu_id, ncores; > > u32 l2ctlr; > > @@ -183,6 +183,12 @@ static void __init tegra_smp_init_cpus(void) > > > > for (i = 0; i < ncores; i++) > > set_cpu_possible(i, true); > > +} > > + > > +static void __init tegra_smp_init_cpus(void) > > +{ > > + if (!num_possible_cpus()) > > + tegra_smp_detect_cores(); > > Thought about this, I would prefer writing an inline function that > provides this information (DT missing /cpu information or parsing failure) > instead of relying on num_possible_cpus to be == 0 as a way to check that. With your "[PATCH] ARM: kernel: DT cpu map validity check helper function", my original patch gets as below. I think that the following "smp_detect_ncores()" function may be so generic that it could be moved in some common place than platform? From f5f2a43952ce75fe061b3808b994c3ceb07f1af1 Mon Sep 17 00:00:00 2001 From: Hiroshi Doyu Date: Mon, 26 Nov 2012 12:25:14 +0200 Subject: [PATCH 1/1] ARM: tegra: # of CPU cores detection w/ & w/o HAVE_ARM_SCU The method to detect the number of CPU cores on Cortex-A9 MPCore and Cortex-A15 MPCore is different. On Cortex-A9 MPCore we can get this information from the Snoop Control Unit(SCU). On Cortex-A15 MPCore we have to read it from the system coprocessor(CP15), because the SCU on Cortex-A15 MPCore does not have software readable registers. This patch selects the correct method at runtime based on the CPU ID. Signed-off-by: Hiroshi Doyu --- arch/arm/mach-tegra/platsmp.c | 54 ++++++++++++++++++++++++++++++++--------- 1 file changed, 43 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 6867030..9a1324a 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include @@ -38,7 +40,7 @@ extern void tegra_secondary_startup(void); static cpumask_t tegra_cpu_init_mask; -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); +static void __iomem *scu_base; #define EVP_CPU_RESET_VECTOR \ (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) @@ -177,23 +179,52 @@ done: return status; } +static int __init smp_detect_ncores(void) +{ + unsigned int ncores, mpidr; + u32 l2ctlr; + phys_addr_t pa; + + mpidr = read_cpuid_mpidr(); + switch (mpidr) { + case ARM_CPU_PART_CORTEX_A15: + asm("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); + ncores = ((l2ctlr >> 24) & 3) + 1; + break; + case ARM_CPU_PART_CORTEX_A9: + /* Get SCU physical base */ + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa)); + scu_base = IO_ADDRESS(pa); + ncores = scu_get_core_count(scu_base); + break; + default: + pr_warn("Unsupported mpidr\n"); + ncores = 1; + break; + } + + return ncores; +} + /* * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ static void __init tegra_smp_init_cpus(void) { - unsigned int i, ncores = scu_get_core_count(scu_base); - - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; + if (!arm_dt_cpu_map_valid()) { + unsigned int i, ncores; + + ncores = smp_detect_ncores(); + if (ncores > nr_cpu_ids) { + pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", + ncores, nr_cpu_ids); + ncores = nr_cpu_ids; + } + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); } - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); - set_smp_cross_call(gic_raise_softirq); } @@ -202,7 +233,8 @@ static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) /* Always mark the boot CPU (CPU0) as initialized. */ cpumask_set_cpu(0, &tegra_cpu_init_mask); - scu_enable(scu_base); + if (scu_base) + scu_enable(scu_base); } struct smp_operations tegra_smp_ops __initdata = {