From patchwork Mon Jan 14 10:43:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 1971901 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id DEBB9DF23A for ; Mon, 14 Jan 2013 10:46:29 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TuhW3-0007ow-Dj; Mon, 14 Jan 2013 10:43:43 +0000 Received: from hqemgate04.nvidia.com ([216.228.121.35]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TuhW0-0007oO-Dj for linux-arm-kernel@lists.infradead.org; Mon, 14 Jan 2013 10:43:41 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Mon, 14 Jan 2013 02:43:20 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 14 Jan 2013 02:43:31 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 14 Jan 2013 02:43:31 -0800 Received: from deemhub01.nvidia.com (10.21.69.137) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.279.1; Mon, 14 Jan 2013 02:43:35 -0800 Received: from DEMAIL01.nvidia.com ([10.21.69.140]) by deemhub01.nvidia.com ([10.21.69.137]) with mapi; Mon, 14 Jan 2013 11:43:33 +0100 From: Hiroshi Doyu To: "robherring2@gmail.com" Date: Mon, 14 Jan 2013 11:43:30 +0100 Subject: Re: [PATCH 4/4] ARM: tegra: Set SCU base address dynamically from DT Thread-Topic: [PATCH 4/4] ARM: tegra: Set SCU base address dynamically from DT Thread-Index: Ac3yQ/9+Oot/FTQWSaKmTO/ZwDeyaQ== Message-ID: <20130114.124330.851549576173829665.hdoyu@nvidia.com> References: <1355725087-11363-1-git-send-email-hdoyu@nvidia.com><1355725087-11363-4-git-send-email-hdoyu@nvidia.com><50CF258E.2080207@gmail.com> In-Reply-To: <50CF258E.2080207@gmail.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-nvconfidentiality: public acceptlanguage: en-US MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130114_054340_639106_D69A389C X-CRM114-Status: GOOD ( 31.07 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.35 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: "linux@arm.linux.org.uk" , "linux-doc@vger.kernel.org" , "devicetree-discuss@lists.ozlabs.org" , "swarren@wwwdotorg.org" , "linux-kernel@vger.kernel.org" , "rob.herring@calxeda.com" , "grant.likely@secretlab.ca" , "rob@landley.net" , "linux-tegra@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Rob Herring wrote @ Mon, 17 Dec 2012 15:00:46 +0100: > On 12/17/2012 12:18 AM, Hiroshi Doyu wrote: > > Set Snoop Control Unit(SCU) register base address dynamically from DT. > > > > Signed-off-by: Hiroshi Doyu > > --- > > arch/arm/mach-tegra/platsmp.c | 23 ++++++++++++++++++++--- > > 1 file changed, 20 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c > > index 1b926df..45c0b79 100644 > > --- a/arch/arm/mach-tegra/platsmp.c > > +++ b/arch/arm/mach-tegra/platsmp.c > > @@ -18,6 +18,8 @@ > > #include > > #include > > #include > > +#include > > +#include > > > > #include > > #include > > @@ -36,7 +38,7 @@ > > > > extern void tegra_secondary_startup(void); > > > > -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); > > +static void __iomem *scu_base; > > > > #define EVP_CPU_RESET_VECTOR \ > > (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) > > @@ -143,14 +145,28 @@ done: > > return status; > > } > > > > +static const struct of_device_id cortex_a9_scu_match[] __initconst = { > > + { .compatible = "arm,cortex-a9-scu", }, > > + {} > > +}; > > + > > /* > > * Initialise the CPU possible map early - this describes the CPUs > > * which may be present or become present in the system. > > */ > > static void __init tegra_smp_init_cpus(void) > > { > > - unsigned int i, ncores = scu_get_core_count(scu_base); > > + struct device_node *np; > > + unsigned int i, ncores = 1; > > + > > + np = of_find_matching_node(NULL, cortex_a9_scu_match); > > + if (!np) > > + return; > > + scu_base = of_iomap(np, 0); > > Did you actually test this? Unless something changed, ioremap does not > work this early. The only reason to have it mapped this early is to get > the core count, but that doesn't work on A15 or A7. So we really need to > get core count/mask in a standard way. At least some work to get core > count from DT went into 3.8. > > BTW, you can get the scu address on the A9 by reading cp15 register: > > /* Get SCU base */ > asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); > > It's still probably good to have the DT node, but the reg property can > be optional in this case. > > We need to move away from having the DT matching code within the > platforms. This should all be moved to the scu code in a scu_of_init > function that could be called from common code. If we can get SCU base address from CP15, do we still need SCU entry in DT? If not, the following would be the only API to get SCU base? From 9bbecb50759f39d9c762977145407ea4f8a4d5ac Mon Sep 17 00:00:00 2001 From: Hiroshi Doyu Date: Mon, 14 Jan 2013 12:35:33 +0200 Subject: [PATCH 1/1] ARM: Add API to detect SCU base address from CP15 Add API to detect SCU base address from CP15. Signed-off-by: Hiroshi Doyu --- arch/arm/include/asm/smp_scu.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index 4eb6d00..6015ede 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -6,6 +6,20 @@ #define SCU_PM_POWEROFF 3 #ifndef __ASSEMBLER__ +static inline phys_addr_t scu_get_base(void) +{ + phys_addr_t pa; + unsigned long part_number = read_cpuid_part_number(); + + switch (part_number) { + case ARM_CPU_PART_CORTEX_A9: + /* Get SCU physical base */ + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa)); + return pa; + default: + return 0; + } +} unsigned int scu_get_core_count(void __iomem *); void scu_enable(void __iomem *); int scu_power_mode(void __iomem *, unsigned int);