From patchwork Fri Jan 18 10:54:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 2073671 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 32B76DF2E5 for ; Thu, 31 Jan 2013 13:03:35 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U0tlL-0000tC-H3; Thu, 31 Jan 2013 13:01:07 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tw9az-0001zH-Lg for linux-arm-kernel@lists.infradead.org; Fri, 18 Jan 2013 10:54:50 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Fri, 18 Jan 2013 02:58:55 -0800 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 18 Jan 2013 02:54:37 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 18 Jan 2013 02:54:37 -0800 Received: from deemhub02.nvidia.com (10.21.69.138) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.297.1; Fri, 18 Jan 2013 02:54:45 -0800 Received: from DEMAIL01.nvidia.com ([10.21.69.139]) by deemhub02.nvidia.com ([10.21.69.138]) with mapi; Fri, 18 Jan 2013 11:54:42 +0100 From: Hiroshi Doyu To: "linux-arm-kernel@lists.infradead.org" Date: Fri, 18 Jan 2013 11:54:40 +0100 Subject: [RESEND][v3 4/9] ARM: Add API to detect SCU base address from CP15 Thread-Topic: [v3 4/9] ARM: Add API to detect SCU base address from CP15 Thread-Index: Ac3y+EgS+TwiZKEUQYSiHKOtXKG4Mw== Message-ID: <20130118.125440.65456178743324707.hdoyu@nvidia.com> References: <1358237598-32413-1-git-send-email-hdoyu@nvidia.com> In-Reply-To: <1358237598-32413-1-git-send-email-hdoyu@nvidia.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-nvconfidentiality: public acceptlanguage: en-US MIME-Version: 1.0 X-Bad-Reply: References and In-Reply-To but no 'Re:' in Subject. X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130118_055449_844440_3F6121CD X-CRM114-Status: UNSURE ( 9.73 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-Mailman-Approved-At: Thu, 31 Jan 2013 07:54:32 -0500 Cc: "linux-tegra@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "rob.herring@calxeda.com" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add API to detect SCU base address from CP15. Signed-off-by: Hiroshi Doyu --- NOTE: This wasn't delivered to linux-arm-kernel@lists.infradead.org, resending.... For usage: http://patchwork.ozlabs.org/patch/212013/ --- arch/arm/include/asm/smp_scu.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index 4eb6d00..f619eef 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -6,6 +6,23 @@ #define SCU_PM_POWEROFF 3 #ifndef __ASSEMBLER__ + +#include + +static inline phys_addr_t scu_get_base(void) +{ + phys_addr_t pa; + unsigned long part_number = read_cpuid_part_number(); + + switch (part_number) { + case ARM_CPU_PART_CORTEX_A9: + /* Get SCU physical base */ + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa)); + return pa; + default: + return 0; + } +} unsigned int scu_get_core_count(void __iomem *); void scu_enable(void __iomem *); int scu_power_mode(void __iomem *, unsigned int);