From patchwork Wed Mar 20 14:00:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Machek X-Patchwork-Id: 2307801 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 97205DF24C for ; Wed, 20 Mar 2013 14:03:30 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UIJZ9-00037E-Rm; Wed, 20 Mar 2013 14:00:31 +0000 Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UIJYt-00036k-JU for linux-arm-kernel@lists.infradead.org; Wed, 20 Mar 2013 14:00:20 +0000 Received: by atrey.karlin.mff.cuni.cz (Postfix, from userid 512) id AA763811CB; Wed, 20 Mar 2013 15:00:14 +0100 (CET) Date: Wed, 20 Mar 2013 15:00:09 +0100 From: Pavel Machek To: dinguyen@altera.com Subject: Re: [PATCHv2 2/2] ARM: socfpga: Add clock entries into device tree Message-ID: <20130320140009.GA27880@amd.pavel.ucw.cz> References: <1363707936-17769-1-git-send-email-dinguyen@altera.com> <1363707936-17769-2-git-send-email-dinguyen@altera.com> <20130320134612.GA27793@amd.pavel.ucw.cz> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20130320134612.GA27793@amd.pavel.ucw.cz> User-Agent: Mutt/1.5.20 (2009-06-14) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130320_100015_750437_3D61BE50 X-CRM114-Status: GOOD ( 15.20 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [195.113.26.193 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: dinh.linux@gmail.com, arnd@arndb.de, olof@lixom.net, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Hi! > > Adds the main PLL clock groups for SOCFPGA into device tree file > > so that the clock framework to query the clock and clock rates > > appropriately. > > Is there an easy way to test it? Please consider cleanups below. If compiles and NFS root fails the same way it failed below. Thanks, Pavel commit 82158c4cf015e3b8c3db1b5ba84722fe1a480dce Author: Pavel Machek Date: Wed Mar 20 14:56:56 2013 +0100 Convert clock_manager_base_addr to structure, to get type checking and nicer code. Improve constants alignment a bit. Signed-off-by: Pavel Machek diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 856625a..b88b992 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -30,7 +30,7 @@ void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); void __iomem *sys_manager_base_addr; void __iomem *rst_manager_base_addr; -void __iomem *clk_mgr_base_addr; +struct clock_manager_hw __iomem *clk_mgr_base_addr; unsigned long cpu1start_addr; static struct map_desc scu_io_desc __initdata = { diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c index 3504dbf..0239ff5 100644 --- a/drivers/clk/socfpga/clk.c +++ b/drivers/clk/socfpga/clk.c @@ -17,16 +17,13 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ + #include #include #include #include #include -/* Clock Manager offsets */ -#define CLKMGR_CTRL 0x0 -#define CLKMGR_BYPASS 0x4 - /* Clock bypass bits */ #define MAINPLL_BYPASS (1<<0) #define SDRAMPLL_BYPASS (1<<1) @@ -37,12 +34,17 @@ #define SOCFPGA_PLL_BG_PWRDWN 0x00000001 #define SOCFPGA_PLL_EXT_ENA 0x00000002 #define SOCFPGA_PLL_PWR_DOWN 0x00000004 -#define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8 +#define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8 #define SOCFPGA_PLL_DIVF_SHIFT 3 -#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 +#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 #define SOCFPGA_PLL_DIVQ_SHIFT 15 -extern void __iomem *clk_mgr_base_addr; +struct clock_manager_hw { + u32 ctrl; + u32 bypass; +}; + +extern struct clock_manager_hw __iomem *clk_mgr_base_addr; struct socfpga_clk { struct clk_hw hw; @@ -83,7 +85,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, unsigned long bypass; reg = readl(socfpgaclk->reg); - bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); + bypass = readl(&clk_mgr_base_addr->bypass); if (bypass & MAINPLL_BYPASS) return parent_rate;