From patchwork Wed Mar 20 14:36:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 2307991 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id D7F7A40213 for ; Wed, 20 Mar 2013 14:33:41 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UIK2y-0005ok-QI; Wed, 20 Mar 2013 14:31:20 +0000 Received: from mail-da0-x236.google.com ([2607:f8b0:400e:c00::236]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UIK2L-0005b7-DD for linux-arm-kernel@lists.infradead.org; Wed, 20 Mar 2013 14:30:42 +0000 Received: by mail-da0-f54.google.com with SMTP id p1so1020633dad.13 for ; Wed, 20 Mar 2013 07:30:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:date:message-id:in-reply-to:references :subject; bh=qF8kTWTneAcVy+UFwxPhTmniV2tJRDjaxMicCr/4+QA=; b=uu4LDeH7GeGCU4U3qNU0xFNK2d1t+o3dI6u+Nea8rEKMgbUFV3Oy0bvkp5AYOH+k13 rxpEfoY1MRcou/LJS4sKu81ZrBfIUgOGh/12v5SwFnL+iINKZzlUZRon3YUS6nUPE9/a 0wJRJK/wXMDk7hlsx7UShbFdTuXx4Ad2g/M2v40KA/SHehpDODestfGL25GpdFGgETaa eG7vOpG4pnd1sHgTBYxTohNwFICvInRmRWmjeRavu/gaTHSena0FTwG4FoUclLf9BlyA 2APg1Oj6iS0tljXcwctzQP938LzdnWyXIjtct/IvCpK0Y0/95pvautCOCuulPiO5v1zl p5Dw== X-Received: by 10.68.189.42 with SMTP id gf10mr9310588pbc.149.1363789839554; Wed, 20 Mar 2013 07:30:39 -0700 (PDT) Received: from [127.0.0.1] (FLH1All083.tky.mesh.ad.jp. [211.13.49.83]) by mx.google.com with ESMTPS id vd4sm2304703pbc.35.2013.03.20.07.30.36 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 20 Mar 2013 07:30:38 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Date: Wed, 20 Mar 2013 23:36:33 +0900 Message-Id: <20130320143633.32377.51612.sendpatchset@w520> In-Reply-To: <20130320143604.32377.32634.sendpatchset@w520> References: <20130320143604.32377.32634.sendpatchset@w520> Subject: [PATCH 03/04] ARM: shmobile: r8a7790 IRQC support X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130320_103041_583399_205BA186 X-CRM114-Status: GOOD ( 12.18 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (magnus.damm[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: kuninori.morimoto.gx@renesas.com, arnd@arndb.de, Magnus Damm , horms@verge.net.au, olof@lixom.net, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Magnus Damm Add IRQC interrupt controller support to r8a7790 by hooking up a single IRQC instances to handle 4 external IRQ signals. The IRQC controller is tied to SPIs of the GIC. On r8a7790 the external IRQ pins routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: Magnus Damm --- Depends on: [PATCH] irqchip: Renesas IRQC driver [PATCH] irqchip: irqc: Add DT support arch/arm/boot/dts/r8a7790.dtsi | 9 +++++++++ arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/setup-r8a7790.c | 21 +++++++++++++++++++++ 3 files changed, 31 insertions(+) --- 0012/arch/arm/boot/dts/r8a7790.dtsi +++ work/arch/arm/boot/dts/r8a7790.dtsi 2013-03-20 22:56:52.000000000 +0900 @@ -51,4 +51,13 @@ <1 11 0xf08>, <1 10 0xf08>; }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe61c0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; + }; }; --- 0012/arch/arm/mach-shmobile/Kconfig +++ work/arch/arm/mach-shmobile/Kconfig 2013-03-20 22:56:52.000000000 +0900 @@ -49,6 +49,7 @@ config ARCH_R8A7790 select CPU_V7 select ARM_ARCH_TIMER select SH_CLK_CPG + select RENESAS_IRQC config ARCH_EMEV2 bool "Emma Mobile EV2" --- 0013/arch/arm/mach-shmobile/setup-r8a7790.c +++ work/arch/arm/mach-shmobile/setup-r8a7790.c 2013-03-20 22:57:09.000000000 +0900 @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -74,6 +75,25 @@ static inline void r8a7790_register_scif sizeof(struct plat_sci_port)); } +static struct renesas_irqc_config irqc0_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ +}; + +static struct resource irqc0_resources[] = { + DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ + DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ +}; + +#define r8a7790_register_irqc(idx) \ + platform_device_register_resndata(&platform_bus, "renesas_irqc", \ + idx, irqc##idx##_resources, \ + ARRAY_SIZE(irqc##idx##_resources), \ + &irqc##idx##_data, \ + sizeof(struct renesas_irqc_config)) + void __init r8a7790_add_standard_devices(void) { r8a7790_register_scif(SCIFA0); @@ -84,6 +104,7 @@ void __init r8a7790_add_standard_devices r8a7790_register_scif(SCIFA2); r8a7790_register_scif(SCIF0); r8a7790_register_scif(SCIF1); + r8a7790_register_irqc(0); } #ifdef CONFIG_USE_OF