From patchwork Thu May 30 08:52:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 2634141 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id D29E1DF2A1 for ; Thu, 30 May 2013 08:48:32 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UhyV4-0004Ue-3a; Thu, 30 May 2013 08:46:26 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UhyUU-0001f6-W6; Thu, 30 May 2013 08:45:47 +0000 Received: from mail-pb0-x234.google.com ([2607:f8b0:400e:c01::234]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UhyUF-0001c4-QD for linux-arm-kernel@lists.infradead.org; Thu, 30 May 2013 08:45:32 +0000 Received: by mail-pb0-f52.google.com with SMTP id xa12so307565pbc.39 for ; Thu, 30 May 2013 01:45:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=8xr4EwEXPuJLvaKKpzuSE09mohrEyV05f/JKCgdogYE=; b=HlyDNsl9zJm76OMvT1PGfB9AEWA7CU+wZ5rD51AZim03GWr4jMqOfuu3bNJjSBL53F XW7EvfltND9gNLXBljwDLvC5ZO2SydHhtdkHmKR/2gSoT2VH8rIHD05TZ69qHJY1UvB8 aUya5w8pFqn+a3NJLQ5wJ8wOuHbphtfw3/Kvwo8vDGnBSbShGxRIh9O5KZHe0c/ayDqK BM3koPHnC3ISpOLmJRw858z043i5GXSv5ue03t+Gq7wa1JIeK04UWgPiwTO6DnqhPbxz 3obwpBrRA2d4LLMqF+9a2c2g80O74Uiy/jd0LJVbnbuMkOPE1Kqr2tV7RT73pAOUro60 K8Dw== X-Received: by 10.66.157.5 with SMTP id wi5mr7582215pab.33.1369903510925; Thu, 30 May 2013 01:45:10 -0700 (PDT) Received: from [127.0.0.1] (49.14.32.202.bf.2iij.net. [202.32.14.49]) by mx.google.com with ESMTPSA id gh9sm40995037pbc.37.2013.05.30.01.45.08 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 May 2013 01:45:09 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Date: Thu, 30 May 2013 17:52:30 +0900 Message-Id: <20130530085230.24374.41041.sendpatchset@w520> In-Reply-To: <20130530085152.24374.64208.sendpatchset@w520> References: <20130530085152.24374.64208.sendpatchset@w520> Subject: [PATCH 04/05] ARM: shmobile: r8a73a4 SMP CA7 prototype (+ CA7 x 4) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130530_044531_974454_4B2CE9F9 X-CRM114-Status: GOOD ( 14.84 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (magnus.damm[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: arnd@arndb.de, Magnus Damm , horms@verge.net.au, ulrich.hecht@gmail.com, olof@lixom.net, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Magnus Damm Prototype code to enable 4 x CA7 found in r8a73a4. To test on APE6EVM boot with maxcpus=4 and use CPU Hotplug for boot and shut down. Not ready for merge. Not-yet-Signed-off-by: Magnus Damm --- arch/arm/boot/dts/r8a73a4.dtsi | 28 ++++++++++++++++++++++++++ arch/arm/mach-shmobile/smp-r8a73a4.c | 36 +++++++++++++++++++++++++++++----- 2 files changed, 59 insertions(+), 5 deletions(-) --- 0002/arch/arm/boot/dts/r8a73a4.dtsi +++ work/arch/arm/boot/dts/r8a73a4.dtsi 2013-05-30 16:13:11.000000000 +0900 @@ -46,6 +46,34 @@ reg = <3>; clock-frequency = <1500000000>; }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <1000000000>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <1000000000>; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <1000000000>; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <1000000000>; + }; }; gic: interrupt-controller@f1001000 { --- 0004/arch/arm/mach-shmobile/smp-r8a73a4.c +++ work/arch/arm/mach-shmobile/smp-r8a73a4.c 2013-05-30 16:18:40.000000000 +0900 @@ -31,17 +31,22 @@ #include #define SYSC 0xe6180000 +#define CA7BAR 0x4020 #define CA15BAR 0x6020 #define RESCNT 0x801c #define APMU 0xe6150000 +#define CA7WUPCR 0x1010 #define CA15WUPCR 0x2010 +#define CA7PSTR 0x1040 #define CA15PSTR 0x2040 +#define CA7CPUNCR(n) (0x1100 + (0x10 * (n))) #define CA15CPUNCR(n) (0x2100 + (0x10 * (n))) #define MERAM 0xe8080000 #define CCI_BASE 0xf0190000 #define CCI_SLAVE3 0x4000 +#define CCI_SLAVE4 0x5000 #define CCI_SNOOP 0x0000 #define CCI_STATUS 0x000c @@ -75,13 +80,16 @@ static void __init r8a73a4_smp_prepare_c p = ioremap_nocache(SYSC, 0x9000); bar = (MERAM >> 8) & 0xfffffc00; __raw_writel(bar, p + CA15BAR); + __raw_writel(bar, p + CA7BAR); __raw_writel(bar | 0x10, p + CA15BAR); + __raw_writel(bar | 0x10, p + CA7BAR); __raw_writel(__raw_readl(p + RESCNT) & ~(1 << 10), p + RESCNT); iounmap(p); /* enable snoop and DVM */ p = ioremap_nocache(CCI_BASE, 0x8000); __raw_writel(3, p + CCI_SLAVE3 + CCI_SNOOP); /* ca15 */ + __raw_writel(3, p + CCI_SLAVE4 + CCI_SNOOP); /* ca7 */ while (__raw_readl(p + CCI_STATUS)) /* wait for pending bit low */; iounmap(p); @@ -92,10 +100,14 @@ static void __init r8a73a4_smp_prepare_c static int __cpuinit r8a73a4_boot_secondary(unsigned int cpu, struct task_struct *idle) { void __iomem *p; + int cluster_cpu = cpu_logical_map(cpu) & 3; /* wake up CPU core */ p = ioremap_nocache(APMU, 0x3000); - __raw_writel(1 << (cpu_logical_map(cpu) & 3), p + CA15WUPCR); + if (cpu_logical_map(cpu) < 4) + __raw_writel(1 << cluster_cpu, p + CA15WUPCR); + else + __raw_writel(1 << cluster_cpu, p + CA7WUPCR); iounmap(p); return 0; @@ -112,6 +124,7 @@ static void __cpuinit r8a73a4_secondary_ static int r8a73a4_cpu_kill(unsigned int cpu) { void __iomem *p; + int offs; int ret = 0; int k; @@ -120,9 +133,18 @@ static int r8a73a4_cpu_kill(unsigned int */ p = ioremap_nocache(APMU, 0x3000); for (k = 0; k < 1000; k++) { - if (((__raw_readl(p + CA15PSTR) >> (cpu * 4)) & 0x03) == 3) { - ret = 1; - break; + if (cpu < 4) { /* CA15 Core Standby */ + offs = cpu * 4; + if (((__raw_readl(p + CA15PSTR) >> offs) & 0x03) == 3) { + ret = 1; + break; + } + } else { /* CA7 Core Standby */ + offs = (cpu - 4) * 4; + if (((__raw_readl(p + CA7PSTR) >> offs) & 0x03) == 3) { + ret = 1; + break; + } } mdelay(1); @@ -176,7 +198,11 @@ static void r8a73a4_cpu_die(unsigned int /* select CPU shutdown mode */ p = ioremap_nocache(APMU, 0x3000); - __raw_writel(3, p + CA15CPUNCR(cpu)); /* CA15 Core Standby */ + if (cpu < 4) + __raw_writel(3, p + CA15CPUNCR(cpu)); /* CA15 Core Standby */ + else + __raw_writel(3, p + CA7CPUNCR(cpu - 4)); /* CA7 Core Standby */ + iounmap(p); cpu_enter_lowpower_a15();