From patchwork Tue Jun 4 17:37:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell King - ARM Linux X-Patchwork-Id: 2661311 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 358A9DF2A1 for ; Tue, 4 Jun 2013 17:43:12 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjvFf-0007Fn-T4; Tue, 04 Jun 2013 17:42:33 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjvEy-0003Ym-7w; Tue, 04 Jun 2013 17:41:48 +0000 Received: from caramon.arm.linux.org.uk ([78.32.30.218]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjvEt-0003TI-Rt for linux-arm-kernel@lists.infradead.org; Tue, 04 Jun 2013 17:41:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=caramon; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=YHTK1GDpjBWWFJnpodNXZ7orkryoxItgOexkXs1hw90=; b=Vr5auyc5KG0peHN1UIWJJ8Xz3dtL/4hdk6yWLlBZBBOBfJTxWbi0gqjRH1yB8jzill9tykCUqft7UpfY9GRGSzjtRpNkgUOiVzSLuJE8aMTOGK6vt0O++HZ4BE9Na5SWxRAXR9x1fp6DNz5jK0QGYT08pbDIJq+/7xk3ZSwQHXM=; Received: from n2100.arm.linux.org.uk ([2002:4e20:1eda:1:214:fdff:fe10:4f86]:39384) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1UjvAz-0000Gl-6L; Tue, 04 Jun 2013 18:37:41 +0100 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.76) (envelope-from ) id 1UjvAw-0000Eu-OH; Tue, 04 Jun 2013 18:37:38 +0100 Date: Tue, 4 Jun 2013 18:37:37 +0100 From: Russell King - ARM Linux To: Gregory CLEMENT Subject: Re: [PATCH v2 1/2] ARM PJ4B: Add support for errata 4742 Message-ID: <20130604173737.GZ18614@n2100.arm.linux.org.uk> References: <1370354598-12920-1-git-send-email-gregory.clement@free-electrons.com> <1370354598-12920-2-git-send-email-gregory.clement@free-electrons.com> <20130604145958.GY18614@n2100.arm.linux.org.uk> <51AE21A7.5080907@free-electrons.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <51AE21A7.5080907@free-electrons.com> User-Agent: Mutt/1.5.19 (2009-01-05) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130604_134144_437950_DE05E49C X-CRM114-Status: GOOD ( 20.87 ) X-Spam-Score: -4.8 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [78.32.30.218 listed in list.dnswl.org] -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Lior Amsalem , Thomas Petazzoni , Yehuda Yitschak , Ike Pan , Jason Cooper , Tawfik Bayouk , Andrew Lunn , Dan Frazier , Nicolas Pitre , Will Deacon , Eran Ben-Avi , Nadav Haklai , Maen Suleiman , Shadi Ammouri , Ezequiel Garcia , Jon Masters , Chris Van Hoof , Sebastian Hesselbarth , David Marlin , linux-arm-kernel@lists.infradead.org, Leif Lindholm X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Tue, Jun 04, 2013 at 07:19:35PM +0200, Gregory CLEMENT wrote: > At least we can detect the PJ4B and maybe even the detect the if it > is the PJ4B or the PJ4B-MP. > > Do you mean to add this test in the cpu_v7_do_idle() function? > > Or patching the pointer to the cpu_v7_do_idle() on the fly? In this > last case it seems a little tricky to me, as we should have to modify > a pointer function in the .proc.info.init section. No. We already have a pj4 cpu type entry in the tables, so we just need to specify a separate set of processor functions. This isn't 100% trivial to do with the macro-isation of stuff, but here's an attempt (untested): arch/arm/mm/proc-v7-2level.S | 4 ++++ arch/arm/mm/proc-v7-3level.S | 4 ++++ arch/arm/mm/proc-v7.S | 28 +++++++++++++++++++++++++--- 3 files changed, 33 insertions(+), 3 deletions(-) diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 9704097..d03c15c 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -38,6 +38,7 @@ * - we are not using split page tables */ ENTRY(cpu_v7_switch_mm) +ENTRY(cpu_pj4b_switch_mm) #ifdef CONFIG_MMU mov r2, #0 mmid r1, r1 @ get mm->context.id @@ -61,6 +62,7 @@ ENTRY(cpu_v7_switch_mm) #endif mov pc, lr ENDPROC(cpu_v7_switch_mm) +ENDPROC(cpu_pj4b_switch_mm) /* * cpu_v7_set_pte_ext(ptep, pte) @@ -73,6 +75,7 @@ ENDPROC(cpu_v7_switch_mm) * - ext - value for extended PTE bits */ ENTRY(cpu_v7_set_pte_ext) +ENTRY(cpu_pj4b_set_pte_ext) #ifdef CONFIG_MMU str r1, [r0] @ linux version @@ -115,6 +118,7 @@ ENTRY(cpu_v7_set_pte_ext) #endif mov pc, lr ENDPROC(cpu_v7_set_pte_ext) +ENDPROC(cpu_pj4b_set_pte_ext) /* * Memory region attributes with SCTLR.TRE=1 diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 363027e..2d819ff 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -46,6 +46,7 @@ * the new TTB). */ ENTRY(cpu_v7_switch_mm) +ENTRY(cpu_pj4b_switch_mm) #ifdef CONFIG_MMU mmid r1, r1 @ get mm->context.id asid r3, r1 @@ -55,6 +56,7 @@ ENTRY(cpu_v7_switch_mm) #endif mov pc, lr ENDPROC(cpu_v7_switch_mm) +ENDPROC(cpu_pj4b_switch_mm) /* * cpu_v7_set_pte_ext(ptep, pte) @@ -64,6 +66,7 @@ ENDPROC(cpu_v7_switch_mm) * - pte - PTE value to store (64-bit in r2 and r3) */ ENTRY(cpu_v7_set_pte_ext) +ENTRY(cpu_pj4b_set_pte_ext) #ifdef CONFIG_MMU tst r2, #L_PTE_VALID beq 1f @@ -78,6 +81,7 @@ ENTRY(cpu_v7_set_pte_ext) #endif mov pc, lr ENDPROC(cpu_v7_set_pte_ext) +ENDPROC(cpu_pj4b_set_pte_ext) /* * Memory region attributes for LPAE (defined in pgtable-3level.h): diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 2c73a73..9964e84 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -26,16 +26,20 @@ #endif ENTRY(cpu_v7_proc_init) +ENTRY(cpu_pj4b_proc_init) mov pc, lr ENDPROC(cpu_v7_proc_init) +ENDPROC(cpu_pj4b_proc_init) ENTRY(cpu_v7_proc_fin) +ENTRY(cpu_pj4b_proc_fin) mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x0006 @ .............ca. mcr p15, 0, r0, c1, c0, 0 @ disable caches mov pc, lr ENDPROC(cpu_v7_proc_fin) +ENDPROC(cpu_pj4b_proc_fin) /* * cpu_v7_reset(loc) @@ -52,6 +56,7 @@ ENDPROC(cpu_v7_proc_fin) .align 5 .pushsection .idmap.text, "ax" ENTRY(cpu_v7_reset) +ENTRY(cpu_pj4b_reset) mrc p15, 0, r1, c1, c0, 0 @ ctrl register bic r1, r1, #0x1 @ ...............m THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) @@ -59,6 +64,7 @@ ENTRY(cpu_v7_reset) isb bx r0 ENDPROC(cpu_v7_reset) +ENDPROC(cpu_pj4b_reset) .popsection /* @@ -74,7 +80,17 @@ ENTRY(cpu_v7_do_idle) mov pc, lr ENDPROC(cpu_v7_do_idle) +ENTRY(cpu_pj4b_do_idle) + dsb + wfi +#ifdef CONFIG_PJ4B_ERRATA_4742 + dsb +#endif + mov pc, lr +ENDPROC(cpu_pj4b_do_idle) + ENTRY(cpu_v7_dcache_clean_area) +ENTRY(cpu_pj4b_dcache_clean_area) ALT_SMP(mov pc, lr) @ MP extensions imply L1 PTW ALT_UP(W(nop)) dcache_line_size r2, r3 @@ -85,6 +101,7 @@ ENTRY(cpu_v7_dcache_clean_area) dsb mov pc, lr ENDPROC(cpu_v7_dcache_clean_area) +ENDPROC(cpu_pj4b_dcache_clean_area) string cpu_v7_name, "ARMv7 Processor" .align @@ -94,6 +111,7 @@ ENDPROC(cpu_v7_dcache_clean_area) .equ cpu_v7_suspend_size, 4 * 8 #ifdef CONFIG_ARM_CPU_SUSPEND ENTRY(cpu_v7_do_suspend) +ENTRY(cpu_pj4b_do_suspend) stmfd sp!, {r4 - r10, lr} mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID @@ -107,8 +125,10 @@ ENTRY(cpu_v7_do_suspend) stmia r0, {r6 - r11} ldmfd sp!, {r4 - r10, pc} ENDPROC(cpu_v7_do_suspend) +ENDPROC(cpu_pj4b_do_suspend) ENTRY(cpu_v7_do_resume) +ENTRY(cpu_pj4b_do_resume) mov ip, #0 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache @@ -138,6 +158,7 @@ ENTRY(cpu_v7_do_resume) mov r0, r8 @ control register b cpu_resume_mmu ENDPROC(cpu_v7_do_resume) +ENDPROC(cpu_pj4b_do_resume) #endif __CPUINIT @@ -350,6 +371,7 @@ __v7_setup_stack: @ define struct processor (see and proc-macros.S) define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 .section ".rodata" @@ -362,7 +384,7 @@ __v7_setup_stack: /* * Standard v7 proc info content */ -.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 +.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ @@ -375,7 +397,7 @@ __v7_setup_stack: .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ HWCAP_EDSP | HWCAP_TLS | \hwcaps .long cpu_v7_name - .long v7_processor_functions + .long proc_fns .long v7wbi_tlb_fns .long v6_user_fns .long v7_cache_fns @@ -411,7 +433,7 @@ __v7_ca9mp_proc_info: __v7_pj4b_proc_info: .long 0x562f5840 .long 0xfffffff0 - __v7_proc __v7_pj4b_setup + __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info /*