From patchwork Tue Jul 9 12:50:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 2825272 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9CB6B9F968 for ; Tue, 9 Jul 2013 12:53:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5EDFA200E1 for ; Tue, 9 Jul 2013 12:53:02 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 04F59200DE for ; Tue, 9 Jul 2013 12:53:01 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UwXNm-0006Mf-Ol; Tue, 09 Jul 2013 12:51:04 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UwXNS-0007Ir-HK; Tue, 09 Jul 2013 12:50:42 +0000 Received: from mail-pd0-x22e.google.com ([2607:f8b0:400e:c02::22e]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UwXNQ-0007Gp-0L for linux-arm-kernel@lists.infradead.org; Tue, 09 Jul 2013 12:50:40 +0000 Received: by mail-pd0-f174.google.com with SMTP id 10so5207825pdc.19 for ; Tue, 09 Jul 2013 05:50:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=kGa+HhdYDeqhMssluxsmN354iwjUEWllU8c+vc13aDw=; b=vApsio4h5OYWZHSdDkaP3y++trE8MeP1NpzkG/VIDyGKzEo/ZtH/lD4YYWtQ9XLtDU rl2jYBaftEtYMV9Qml4ykIO7U9BP9AzMBdLxUykQmgiJryqRZGacdtZrPjtHNrdbyLOM sgTCmIpsO7YOOyLanG1QLuAo3matAPgMA52hhgThuimLoBSmechxAbAoKr1EGOlMaVBW ii3Wy27e/A6iNxf4EiK65A3/+PFEn9H7ELM+qCEKc7hBytiRVeAslF9TJ2Fkm4TY2n7t 7g0wPf5TFPVtD+BwmBBAoeznZ+scUxLwcOzj3ddzRmLDm+40ZjznttZ2Prwt2k9ve9qz 34TQ== X-Received: by 10.66.121.195 with SMTP id lm3mr28108513pab.116.1373374218566; Tue, 09 Jul 2013 05:50:18 -0700 (PDT) Received: from [127.0.0.1] (ac230065.ppp.asahi-net.or.jp. [183.77.230.65]) by mx.google.com with ESMTPSA id wg6sm28164938pbc.3.2013.07.09.05.50.16 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 09 Jul 2013 05:50:17 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Date: Tue, 09 Jul 2013 21:50:24 +0900 Message-Id: <20130709125024.4388.50953.sendpatchset@w520> In-Reply-To: <20130709125007.4388.15701.sendpatchset@w520> References: <20130709125007.4388.15701.sendpatchset@w520> Subject: [PATCH 02/02] ARM: shmobile: Setup r8a7790 arch timer based on MD pins X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130709_085040_146088_578CBB17 X-CRM114-Status: GOOD ( 16.62 ) X-Spam-Score: -2.0 (--) Cc: arnd@arndb.de, Magnus Damm , horms@verge.net.au, ulrich.hecht@gmail.com, olof@lixom.net, shinya.kuribayashi.px@renesas.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Update the r8a7790 arch timer setup code to configure the frequency dynamically at boot time. This means that the arch timer driver will be able to detect a timer frequency that has been calculated based on the MD pins instead of a fixed and potentially incorrect 13 MHz. With this patch applied the Linux kernel will correctly support the r8a7790 Lager board that uses a 20 Mhz EXTAL. The arch timer will operate on 10 MHz and the Linux arch timer driver will be correctly configured to use 10 MHz. Without this patch the 20 MHz EXTAL will be used to drive the arch timer at 10 MHz, but the Linux arch timer driver will believe it is counting at 13 Mhz. Signed-off-by: Magnus Damm --- arch/arm/mach-shmobile/setup-r8a7790.c | 49 ++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 5 deletions(-) --- 0006/arch/arm/mach-shmobile/setup-r8a7790.c +++ work/arch/arm/mach-shmobile/setup-r8a7790.c 2013-07-09 21:29:18.000000000 +0900 @@ -215,14 +215,53 @@ u32 __init r8a7790_read_mode_pins(void) return mode; } +#define CNTCR 0 +#define CNTFID0 0x20 + void __init r8a7790_timer_init(void) { - void __iomem *cntcr; +#ifdef CONFIG_ARM_ARCH_TIMER + u32 mode = r8a7790_read_mode_pins(); + void __iomem *base; + int extal_mhz = 0; + u32 freq; + + /* At Linux boot time the r8a7790 arch timer comes up + * with the counter disabled. Moreover, it may also report + * a potentially incorrect fixed 13 MHz frequency. To be + * correct these registers need to be updated to use the + * frequency EXTAL / 2 which can be determined by the MD pins. + */ + + switch (mode & (MD(14) | MD(13))) { + case 0: + extal_mhz = 15; + break; + case MD(13): + extal_mhz = 20; + break; + case MD(14): + extal_mhz = 26; + break; + case MD(13) | MD(14): + extal_mhz = 30; + break; + } + + /* The arch timer frequency equals EXTAL / 2 */ + freq = extal_mhz * (1000000 / 2); + + /* Remap "armgcnt address map" space */ + base = ioremap(0xe6080000, PAGE_SIZE); + + /* Update registers with correct frequency */ + iowrite32(freq, base + CNTFID0); + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); - /* make sure arch timer is started by setting bit 0 of CNTCT */ - cntcr = ioremap(0xe6080000, PAGE_SIZE); - iowrite32(1, cntcr); - iounmap(cntcr); + /* make sure arch timer is started by setting bit 0 of CNTCR */ + iowrite32(1, base + CNTCR); + iounmap(base); +#endif /* CONFIG_ARM_ARCH_TIMER */ shmobile_timer_init(); }