From patchwork Thu Jul 11 16:22:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 2826565 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1CA31C0AB2 for ; Thu, 11 Jul 2013 17:28:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EFE5E201DD for ; Thu, 11 Jul 2013 17:28:57 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B007F201C3 for ; Thu, 11 Jul 2013 17:28:56 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxJgZ-0001dv-6n; Thu, 11 Jul 2013 16:25:47 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxJdo-0004R6-N1; Thu, 11 Jul 2013 16:22:48 +0000 Received: from mail-pd0-x231.google.com ([2607:f8b0:400e:c02::231]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxJdh-0004ON-JK for linux-arm-kernel@lists.infradead.org; Thu, 11 Jul 2013 16:22:42 +0000 Received: by mail-pd0-f177.google.com with SMTP id p10so7676750pdj.22 for ; Thu, 11 Jul 2013 09:22:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=Y/t3HH/KrQ5QlpDhnW3F+fUSvQLXh107Mf87uNsD2Vs=; b=VcJNKi7NjkD31iLIOSNLlmlnS+V/iQDnXw8uno2uRJ0HXN3UObV5MTORnC7lHVahOR /0CafCcCPq7EOry2v9R0zNsZTon7FagsTZS8DfYkkJqJEUmH13+PF1xx6iVQq7sxRkW3 7VLiodEQHXSP1AoVAIJMPpj8hCvh0WUdRhzoWVDEyVUhyvhnVEuDnq679UhCPPebSaQR AgayMBd4gX76caVXXtiDk7NHW6nx2XamvU8RoIT6F8hOBEr5UKU62WHMUg10UxL5vPGL T9LfU6TSvwVGTrNcWlxlQHd7etRnLZlWSxVUX/vRQR77QqbPd37QnCl6XTaYTLknMXKN 7mag== X-Received: by 10.66.219.1 with SMTP id pk1mr4722177pac.29.1373559744428; Thu, 11 Jul 2013 09:22:24 -0700 (PDT) Received: from [127.0.0.1] (ac230065.ppp.asahi-net.or.jp. [183.77.230.65]) by mx.google.com with ESMTPSA id ry2sm40431594pbc.41.2013.07.11.09.22.21 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Jul 2013 09:22:23 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Date: Fri, 12 Jul 2013 01:22:29 +0900 Message-Id: <20130711162229.933.53924.sendpatchset@w520> In-Reply-To: <20130711162209.933.47610.sendpatchset@w520> References: <20130711162209.933.47610.sendpatchset@w520> Subject: [PATCH 02/02] ARM: shmobile: Setup r8a7790 arch timer based on MD pins X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130711_122241_772311_3AEF0438 X-CRM114-Status: GOOD ( 16.79 ) X-Spam-Score: -2.0 (--) Cc: arnd@arndb.de, Magnus Damm , horms@verge.net.au, ulrich.hecht@gmail.com, olof@lixom.net, shinya.kuribayashi.px@renesas.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Update the r8a7790 arch timer setup code to configure the frequency dynamically at boot time. This means that the arch timer driver will be able to detect a timer frequency that has been calculated based on the MD pins instead of a fixed and potentially incorrect 13 MHz. With this patch applied the Linux kernel will correctly support the r8a7790 Lager board that uses a 20 Mhz EXTAL. The arch timer will operate on 10 MHz and the Linux arch timer driver will be correctly configured to use 10 MHz. Without this patch the 20 MHz EXTAL will be used to drive the arch timer at 10 MHz, but the Linux arch timer driver will believe it is counting at 13 Mhz. Reported-by: Ulrich Hecht Signed-off-by: Magnus Damm Tested-by: Ulrich Hecht --- arch/arm/mach-shmobile/setup-r8a7790.c | 49 ++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 5 deletions(-) --- 0006/arch/arm/mach-shmobile/setup-r8a7790.c +++ work/arch/arm/mach-shmobile/setup-r8a7790.c 2013-07-09 21:29:18.000000000 +0900 @@ -215,14 +215,53 @@ u32 __init r8a7790_read_mode_pins(void) return mode; } +#define CNTCR 0 +#define CNTFID0 0x20 + void __init r8a7790_timer_init(void) { - void __iomem *cntcr; +#ifdef CONFIG_ARM_ARCH_TIMER + u32 mode = r8a7790_read_mode_pins(); + void __iomem *base; + int extal_mhz = 0; + u32 freq; + + /* At Linux boot time the r8a7790 arch timer comes up + * with the counter disabled. Moreover, it may also report + * a potentially incorrect fixed 13 MHz frequency. To be + * correct these registers need to be updated to use the + * frequency EXTAL / 2 which can be determined by the MD pins. + */ + + switch (mode & (MD(14) | MD(13))) { + case 0: + extal_mhz = 15; + break; + case MD(13): + extal_mhz = 20; + break; + case MD(14): + extal_mhz = 26; + break; + case MD(13) | MD(14): + extal_mhz = 30; + break; + } + + /* The arch timer frequency equals EXTAL / 2 */ + freq = extal_mhz * (1000000 / 2); + + /* Remap "armgcnt address map" space */ + base = ioremap(0xe6080000, PAGE_SIZE); + + /* Update registers with correct frequency */ + iowrite32(freq, base + CNTFID0); + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); - /* make sure arch timer is started by setting bit 0 of CNTCT */ - cntcr = ioremap(0xe6080000, PAGE_SIZE); - iowrite32(1, cntcr); - iounmap(cntcr); + /* make sure arch timer is started by setting bit 0 of CNTCR */ + iowrite32(1, base + CNTCR); + iounmap(base); +#endif /* CONFIG_ARM_ARCH_TIMER */ shmobile_timer_init(); }