From patchwork Fri Jul 26 14:56:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Domenico Andreoli X-Patchwork-Id: 2834224 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5090A9F243 for ; Fri, 26 Jul 2013 15:14:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8D54020187 for ; Fri, 26 Jul 2013 15:14:16 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C3DC920184 for ; Fri, 26 Jul 2013 15:14:14 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2ji6-0008UD-IM; Fri, 26 Jul 2013 15:13:40 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2jhq-0006bu-4R; Fri, 26 Jul 2013 15:13:22 +0000 Received: from mail-ea0-x229.google.com ([2a00:1450:4013:c01::229]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2jhL-0006XW-LK for linux-arm-kernel@lists.infradead.org; Fri, 26 Jul 2013 15:12:55 +0000 Received: by mail-ea0-f169.google.com with SMTP id h15so1639294eak.0 for ; Fri, 26 Jul 2013 08:12:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:user-agent:date:from:to:cc:subject:references :content-disposition; bh=ElNT5LER1mXJRJ1igpJ2cI9i9G2McbvDbXndNRxhSwg=; b=rhRf/8oGQuI6Y6vKdHx8eDPfZumPPYvuJ+43XnNNSlon/Ow1uXwPkAFaxFp/4TSI1t 2tFNb+z3BxyE6Qj4QmDVjVXZu4mO/WgnN89uW80Vage1FeRjtuCsRCuZqfFlkpL3dYDZ A0V0dyDdsJ1bogAipqIC5rPPYwlMn0MGRddLVRH8GqlHLLXHxYmsj9lX7+8xaImfLPn4 bNFizMw1gFaZ1mlb4Q3Tm3owerDrbxfZBrQprFSaHODr9fpUs3u8hHSWzYJSOvfOG8Tr dy5UTptL2a7Yh13KQODMG9umbO57CaB8iJccBNyEbPXANY7yV1xlCO8RmSXXEFj1SO+h zAag== X-Received: by 10.15.52.5 with SMTP id o5mr48141111eew.58.1374851548284; Fri, 26 Jul 2013 08:12:28 -0700 (PDT) Received: from shock.dandreoli.com (j115181.upc-j.chello.nl. [24.132.115.181]) by mx.google.com with ESMTPSA id r54sm81532266eev.8.2013.07.26.08.12.25 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 26 Jul 2013 08:12:26 -0700 (PDT) Received: by shock.dandreoli.com (Postfix, from userid 1000) id D71603402E1; Fri, 26 Jul 2013 17:12:23 +0200 (CEST) Message-Id: <20130726151223.607806229@gmail.com> User-Agent: quilt/0.60-1 Date: Fri, 26 Jul 2013 16:56:42 +0200 From: Domenico Andreoli To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/5] ARM: bcm4760: Add system timer References: <20130726145639.116237136@gmail.com> Content-Disposition: inline; filename=arm-bcm476x-add-system-timer.patch X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130726_111251_940762_E69516B0 X-CRM114-Status: GOOD ( 20.01 ) X-Spam-Score: -1.9 (-) Cc: Russell King - ARM Linux , Arnd Bergmann , Domenico Andreoli , John Stultz , Olof Johansson , Thomas Gleixner X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Domenico Andreoli System timer implementation for the BCM4760 based SoCs. v2: * dropped clock-frequency property, its allowed value was anyway fixed to 24MHz and not clearly related to any known clock v1: * initial release Cc: John Stultz Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Domenico Andreoli --- Documentation/devicetree/bindings/timer/brcm,bcm4760-system-timer.txt | 21 + arch/arm/boot/dts/bcm4760.dtsi | 8 + arch/arm/mach-bcm/Kconfig | 1 + drivers/clocksource/Makefile | 1 + drivers/clocksource/bcm4760_timer.c | 163 ++++++++++ 5 files changed, 194 insertions(+) Index: b/Documentation/devicetree/bindings/timer/brcm,bcm4760-system-timer.txt =================================================================== --- /dev/null +++ b/Documentation/devicetree/bindings/timer/brcm,bcm4760-system-timer.txt @@ -0,0 +1,21 @@ +Broadcom BCM4760 System Timer device tree bindings +-------------------------------------------------- + +The BCM4760 Timer peripheral provides either two or four 32-bit timer +channels. Three timer blocks are available at 0xba000, 0xbb000 and +0xd1000. The first two provide four channels, the last (in the AON - +Always ON power domain) provides only two. + +Required properties: + +- compatible : should be "brcm,bcm4760-system-timer" +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 2 or 4 interrupt sinks; one per timer channel. + +Example: + +timer@ba000 { + compatible = "brcm,bcm4760-system-timer"; + reg = <0xba000 0x1000>; + interrupts = <4>, <11>; +}; Index: b/arch/arm/boot/dts/bcm4760.dtsi =================================================================== --- a/arch/arm/boot/dts/bcm4760.dtsi +++ b/arch/arm/boot/dts/bcm4760.dtsi @@ -27,6 +27,14 @@ #size-cells = <1>; ranges; + timer@ba000 { + compatible = "brcm,bcm4760-system-timer"; + reg = <0xba000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <4>, <11>; + clock-frequency = <24000000>; + }; + vic0: interrupt-controller@80000 { compatible = "brcm,bcm4760-pl192", "arm,pl192-vic", "arm,primecell"; reg = <0x80000 0x1000>; Index: b/drivers/clocksource/Makefile =================================================================== --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clk obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o obj-$(CONFIG_ORION_TIMER) += time-orion.o obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o +obj-$(CONFIG_ARCH_BCM4760) += bcm4760_timer.o obj-$(CONFIG_ARCH_MARCO) += timer-marco.o obj-$(CONFIG_ARCH_MXS) += mxs_timer.o obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o Index: b/drivers/clocksource/bcm4760_timer.c =================================================================== --- /dev/null +++ b/drivers/clocksource/bcm4760_timer.c @@ -0,0 +1,163 @@ +/* + * Broadcom BCM4760 based ARM11 SoCs system timer + * + * Copyright (C) 2012 Domenico Andreoli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER_LOAD_OFFSET 0x00 /* load */ +#define TIMER_VALUE_OFFSET 0x04 /* value */ +#define TIMER_CONTROL_OFFSET 0x08 /* control */ +#define TIMER_INTCLR_OFFSET 0x0c /* interrupt clear */ +#define TIMER_RIS_OFFSET 0x10 /* raw interrupt */ +#define TIMER_MIS_OFFSET 0x14 /* masked interrupt status */ +#define TIMER_BGLOAD_OFFSET 0x18 /* background load */ + +#define TIMER_CTRL_ONESHOTMODE BIT(0) /* One shot mode */ +#define TIMER_CTRL_32BIT BIT(1) /* 32-bit counter mode */ +#define TIMER_CTRL_IE BIT(5) /* Interrupt enable */ +#define TIMER_CTRL_PERIODIC BIT(6) /* Periodic mode */ +#define TIMER_CTRL_EN BIT(7) /* Timer enable */ +#define TIMER_CTRL_CLK2 BIT(9) /* Clock 2 selected */ +#define TIMER_CTRL_PREBY16 (1 << 2) /* prescale divide by 16 */ +#define TIMER_CTRL_PREBY256 (2 << 2) /* prescale divide by 256 */ + +struct bcm4760_timer { + void __iomem *base; + struct clock_event_device evt; + struct irqaction act; +}; + +static inline void __iomem *to_load(struct bcm4760_timer *timer) +{ + return timer->base + TIMER_LOAD_OFFSET; +} + +static inline void __iomem *to_control(struct bcm4760_timer *timer) +{ + return timer->base + TIMER_CONTROL_OFFSET; +} + +static inline void __iomem *to_intclr(struct bcm4760_timer *timer) +{ + return timer->base + TIMER_INTCLR_OFFSET; +} + +static inline void __iomem *to_ris(struct bcm4760_timer *timer) +{ + return timer->base + TIMER_RIS_OFFSET; +} + +static inline void __iomem *to_mis(struct bcm4760_timer *timer) +{ + return timer->base + TIMER_MIS_OFFSET; +} + +static void bcm4760_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt_dev) +{ + struct bcm4760_timer *timer; + u32 val; + + timer = container_of(evt_dev, struct bcm4760_timer, evt); + val = TIMER_CTRL_CLK2 | TIMER_CTRL_32BIT | + TIMER_CTRL_IE | TIMER_CTRL_EN; + + switch (mode) { + case CLOCK_EVT_MODE_ONESHOT: + writel(val | TIMER_CTRL_ONESHOTMODE, to_control(timer)); + break; + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_SHUTDOWN: + break; + default: + WARN(1, "%s: unhandled event mode %d\n", __func__, mode); + break; + } +} + +static int bcm4760_timer_set_next_event(unsigned long event, + struct clock_event_device *evt_dev) +{ + struct bcm4760_timer *timer; + + timer = container_of(evt_dev, struct bcm4760_timer, evt); + writel(event, to_load(timer)); + return 0; +} + +static irqreturn_t bcm4760_timer_interrupt(int irq, void *dev_id) +{ + struct bcm4760_timer *timer = dev_id; + void (*event_handler)(struct clock_event_device *); + + /* check the (masked) interrupt status */ + if (!readl_relaxed(to_mis(timer))) + return IRQ_NONE; + + /* clear the timer interrupt */ + writel_relaxed(1, to_intclr(timer)); + + event_handler = ACCESS_ONCE(timer->evt.event_handler); + if (event_handler) + event_handler(&timer->evt); + + return IRQ_HANDLED; +} + +static void __init bcm4760_init_time(struct device_node *node) +{ + void __iomem *base; + u32 freq = 24000000; + int irq; + struct bcm4760_timer *timer; + + base = of_iomap(node, 0); + if (!base) + panic("Can't remap timer registers"); + + timer = kzalloc(sizeof(*timer), GFP_KERNEL); + if (!timer) + panic("Can't allocate timer struct\n"); + + irq = irq_of_parse_and_map(node, 0); + if (irq <= 0) + panic("Can't parse timer IRQ"); + + timer->base = base; + timer->evt.name = node->name; + timer->evt.rating = 300; + timer->evt.features = CLOCK_EVT_FEAT_ONESHOT; + timer->evt.set_mode = bcm4760_timer_set_mode; + timer->evt.set_next_event = bcm4760_timer_set_next_event; + timer->evt.cpumask = cpumask_of(0); + timer->act.name = node->name; + timer->act.flags = IRQF_TIMER | IRQF_SHARED; + timer->act.dev_id = timer; + timer->act.handler = bcm4760_timer_interrupt; + + if (setup_irq(irq, &timer->act)) + panic("Can't set up timer IRQ\n"); + + clockevents_config_and_register(&timer->evt, freq, 0xf, 0xffffffff); +} + +CLOCKSOURCE_OF_DECLARE(bcm4760, "brcm,bcm4760-system-timer", bcm4760_init_time); Index: b/arch/arm/mach-bcm/Kconfig =================================================================== --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -23,4 +23,5 @@ config ARCH_BCM4760 select ARM_AMBA select ARM_VIC select CLKSRC_OF + select GENERIC_CLOCKEVENTS select SOC_BUS