From patchwork Wed Aug 7 22:45:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 2840625 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D84DABF535 for ; Wed, 7 Aug 2013 22:45:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D2EF420208 for ; Wed, 7 Aug 2013 22:45:29 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6FCE201FA for ; Wed, 7 Aug 2013 22:45:28 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V7CTu-0002Hc-Re; Wed, 07 Aug 2013 22:45:27 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V7CTs-0008OB-EO; Wed, 07 Aug 2013 22:45:24 +0000 Received: from mail-pa0-x235.google.com ([2607:f8b0:400e:c03::235]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V7CTo-0008Ne-K8 for linux-arm-kernel@lists.infradead.org; Wed, 07 Aug 2013 22:45:21 +0000 Received: by mail-pa0-f53.google.com with SMTP id lb1so2698652pab.12 for ; Wed, 07 Aug 2013 15:44:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:subject; bh=7Bor6TAge74tMujx3NYRB3OlNMKIM2mZ9RXRRYmaKuA=; b=AvElgX5/iukxgIns3WqiSRwMLDTxr0YO81ejsT0k08worGEkasg9RlRMvpmSzvumnb /G2tPJWc2SIrxy8wzvpKvzAZ/mR2OCZhrT1ickbLJQNURFFhZd+8QHFJH3U9CvR3uh8x 7evAHF1mqPSdldV5beODGxPHiIy23ltE5/d3t3tKEGAZUUQkkvwf/378EYRSFJQdYrqh p0s/j0iacO3GheOIwBl22UEu4DKnc2R3HCfAWc3vO0B9Dzp9sc6JO+nLgs5fKja1vDCS nHEZ6nF0FlsrLcpHt8YzgicSV2H9ikIRk/7eKkQVUJv8iMvoc0rTwwjppWgLLto8AA9B ZF8g== X-Received: by 10.68.137.134 with SMTP id qi6mr2819947pbb.154.1375915498409; Wed, 07 Aug 2013 15:44:58 -0700 (PDT) Received: from [127.0.0.1] (ac230065.ppp.asahi-net.or.jp. [183.77.230.65]) by mx.google.com with ESMTPSA id eq5sm10402132pbc.15.2013.08.07.15.44.55 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 07 Aug 2013 15:44:57 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Date: Thu, 08 Aug 2013 07:45:10 +0900 Message-Id: <20130807224510.9832.38560.sendpatchset@w520> Subject: [PATCH] ARM: shmobile: Shared APMU SMP support code X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130807_184520_849148_0EA2234C X-CRM114-Status: GOOD ( 17.57 ) X-Spam-Score: -2.0 (--) Cc: olof@lixom.net, horms@verge.net.au, Magnus Damm , linux-arm-kernel@lists.infradead.org, arnd@arndb.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Introduce shared APMU SMP code for mach-shmobile. Both SMP boot up and CPU Hotplug is supported. DT is used for configuration of the APMU hardware block, as the following r8a73a4 example shows: apmu@e6152000 { compatible = "renesas,r8a73a4-apmu", "renesas,apmu"; reg = <0 0xe6152000 0 0x88>; cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; }; The code is designed around CONFIG_NR_CPUS and should in theory support any number of APMUs. At this point only the APMU that includes the boot CPU is enabled - this to prevent non-deterministic scheduling on upstream in case of multi-cluster hardware with varying performance. Signed-off-by: Magnus Damm --- Written against renesas.git renesas-devel-20130806v4 and [PATCH 00/05] ARM: shmobile: Yet another SMP series [PATCH 00/02] ARM: shmobile: Rename to r8a73a4/r8a7790_init_early() arch/arm/mach-shmobile/include/mach/common.h | 5 arch/arm/mach-shmobile/platsmp-apmu.c | 197 ++++++++++++++++++++++++++ 2 files changed, 202 insertions(+) --- 0007/arch/arm/mach-shmobile/include/mach/common.h +++ work/arch/arm/mach-shmobile/include/mach/common.h 2013-08-08 07:36:45.000000000 +0900 @@ -22,6 +22,11 @@ extern int shmobile_smp_scu_boot_seconda struct task_struct *idle); extern void shmobile_smp_scu_cpu_die(unsigned int cpu); extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); +extern void shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus); +extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu, + struct task_struct *idle); +extern void shmobile_smp_apmu_cpu_die(unsigned int cpu); +extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu); struct clk; extern int shmobile_clk_init(void); extern void shmobile_handle_irq_intc(struct pt_regs *); --- /dev/null +++ work/arch/arm/mach-shmobile/platsmp-apmu.c 2013-08-08 07:32:45.000000000 +0900 @@ -0,0 +1,197 @@ +/* + * SMP support for SoCs with APMU + * + * Copyright (C) 2013 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct { + void __iomem *iomem; + int bit; +} apmu_cpus[CONFIG_NR_CPUS]; + +#define WUPCR_OFFS 0x10 +#define PSTR_OFFS 0x40 +#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) + +static int apmu_power_on(void __iomem *p, int bit) +{ + /* request power on */ + writel_relaxed(BIT(bit), p + WUPCR_OFFS); + + /* wait for APMU to finish */ + while (readl_relaxed(p + WUPCR_OFFS) != 0) + ; + + return 0; +} + +static int apmu_power_off(void __iomem *p, int bit) +{ + /* request Core Standby for next WFI */ + writel_relaxed(3, p + CPUNCR_OFFS(bit)); + return 0; +} + +static int apmu_power_off_poll(void __iomem *p, int bit) +{ + int k; + + for (k = 0; k < 1000; k++) { + if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3) + return 1; + + mdelay(1); + } + + return 0; +} + +static int apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu)) +{ + void __iomem *p = apmu_cpus[cpu].iomem; + + return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL; +} + +static void apmu_init_cpu(struct device_node *np, int cpu, int bit) +{ + struct resource res; + + if (apmu_cpus[cpu].iomem) + return; + + if (!of_address_to_resource(np, 0, &res)) + apmu_cpus[cpu].iomem = ioremap_nocache(res.start, + resource_size(&res)); + apmu_cpus[cpu].bit = bit; + + pr_debug("apmu ioremap %d %d 0x%08x 0x%08x\n", cpu, bit, + res.start, resource_size(&res)); +} + +static struct of_device_id apmu_ids[] = { + { .compatible = "renesas,apmu" }, + { /*sentinel*/ } +}; + +static void apmu_parse_dt(void (*fn)(struct device_node *np, int cpu, int bit)) +{ + struct device_node *np_apmu, *np_cpu; + u32 id; + int bit, index; + bool is_allowed; + + for_each_matching_node(np_apmu, apmu_ids) { + /* only enable the cluster that includes the boot CPU */ + is_allowed = false; + for (bit = 0; bit < CONFIG_NR_CPUS; bit++) { + np_cpu = of_parse_phandle(np_apmu, "cpus", bit); + if (np_cpu) { + if (!of_property_read_u32(np_cpu, "reg", &id)) { + if (id == cpu_logical_map(0)) + is_allowed = true; + } + of_node_put(np_cpu); + } + } + if (!is_allowed) + continue; + + for (bit = 0; bit < CONFIG_NR_CPUS; bit++) { + np_cpu = of_parse_phandle(np_apmu, "cpus", bit); + if (np_cpu) { + if (!of_property_read_u32(np_cpu, "reg", &id)) { + index = get_logical_index(id); + if (index >= 0) + fn(np_apmu, index, bit); + } + of_node_put(np_cpu); + } + } + of_node_put(np_apmu); + } +} + +void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus) +{ + /* install boot code shared by all CPUs */ + shmobile_boot_fn = virt_to_phys(shmobile_smp_boot); + shmobile_boot_arg = MPIDR_HWID_BITMASK; + + /* perform per-cpu setup */ + apmu_parse_dt(apmu_init_cpu); +} + +int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + /* For this particular CPU register boot vector */ + shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0); + + return apmu_wrap(cpu, apmu_power_on); +} + +#ifdef CONFIG_HOTPLUG_CPU +/* nicked from arch/arm/mach-exynos/hotplug.c */ +static inline void cpu_enter_lowpower_a15(void) +{ + unsigned int v; + + asm volatile( + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "Ir" (CR_C) + : "cc"); + + flush_cache_louis(); + + asm volatile( + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (0x40) + : "cc"); + + isb(); + dsb(); +} + +void shmobile_smp_apmu_cpu_die(unsigned int cpu) +{ + /* For this particular CPU deregister boot vector */ + shmobile_smp_hook(cpu, 0, 0); + + /* Select next sleep mode using the APMU */ + apmu_wrap(cpu, apmu_power_off); + + /* Do ARM specific CPU shutdown */ + cpu_enter_lowpower_a15(); + + /* jump to shared mach-shmobile sleep / reset code */ + shmobile_smp_sleep(); +} + +int shmobile_smp_apmu_cpu_kill(unsigned int cpu) +{ + return apmu_wrap(cpu, apmu_power_off_poll); +} +#endif