From patchwork Tue Aug 13 03:40:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 2843349 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B382A9F271 for ; Tue, 13 Aug 2013 03:41:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D54D620367 for ; Tue, 13 Aug 2013 03:41:44 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D365020357 for ; Tue, 13 Aug 2013 03:41:43 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V95U7-00017x-VG; Tue, 13 Aug 2013 03:41:28 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V95U5-0004Bo-JB; Tue, 13 Aug 2013 03:41:25 +0000 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V95Tz-0004B1-7y for linux-arm-kernel@lists.infradead.org; Tue, 13 Aug 2013 03:41:20 +0000 Received: by mail-pa0-f43.google.com with SMTP id hz10so8297936pad.30 for ; Mon, 12 Aug 2013 20:40:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=CJHDeTOdeD+0KmlydwXP8XG/EiR5AO63ufcjQUwtiHw=; b=O+gp9JOXqQzDy2Rlw06LTPwDjkMFk9OI3SIy+DkN6JSFyIt722Fmc2wtbxbbnl/aWN mJg7VjLRjvlXKaVLEwCZkHTPu+pBtuTxZInuj9f1SHGK9eZ64v6nlRDLjYIZP4FvVn9Y DDDig3EoocAgIpWGr7A64TWnyuqJLvw3m0S3pZVufSog/TSfZx2NFgas376AsiLZBO7I 9WW3i3d6JpTdHk8j5ylvr/MBn3Dj3rlDBIMpUqJZcM3+/AplO+Y/qYPy64X41bEivWvv ibcACiiVrIwynQCZmUEHCOdgH/Xe63RVn7P8NXM8z6dRSCsNPT3mysHYc5NmuK1VUnRg GubQ== X-Received: by 10.66.233.195 with SMTP id ty3mr2329749pac.70.1376365256375; Mon, 12 Aug 2013 20:40:56 -0700 (PDT) Received: from localhost (108-223-40-66.lightspeed.sntcca.sbcglobal.net. [108.223.40.66]) by mx.google.com with ESMTPSA id ll5sm43619307pab.19.2013.08.12.20.40.54 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 12 Aug 2013 20:40:55 -0700 (PDT) Date: Mon, 12 Aug 2013 20:40:54 -0700 From: Guenter Roeck To: Peter Maydell Subject: Re: [Qemu-devel] SCSI bus failures with qemu-arm in kernel 3.8+ Message-ID: <20130813034054.GA18218@roeck-us.net> References: <5207B3C3.9080508@roeck-us.net> <20130811220450.GY23006@n2100.arm.linux.org.uk> <52082EF8.10005@roeck-us.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130812_234119_382841_40CD462D X-CRM114-Status: GOOD ( 19.72 ) X-Spam-Score: -1.6 (-) Cc: Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , qemu-devel@nongnu.org, Paul Gortmaker , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Mon, Aug 12, 2013 at 05:24:50PM +0100, Peter Maydell wrote: [ ... ] > If somebody would like to fix the kernel I am happy to > locate the PCI backplane and test everything (again). > I would suggest that producing some patches which work > with QEMU 1.5 or later would be a good start; then we > can test on h/w as confirmation before they are applied. > Ok, putting a stake in the ground. Patch tested and working with qemu 1.5.2, using the configuration file from the yocto project. Patch applied on top of kernel version 3.11-rc5. Guenter --- From 1e07521e935267f2d63ed3635fb93c7e325e0936 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Mon, 12 Aug 2013 16:20:18 -0700 Subject: [PATCH] arm: Fix map_irq function for ARM versatile hardware Booting the ARM versatile in qemu fails with the SCSI controller timing out as follows: ------------ sym0: <895a> rev 0x0 at pci 0000:00:0d.0 irq 92 sym0: SCSI BUS has been reset. scsi0 : sym-2.2.3 [...] scsi 0:0:0:0: ABORT operation started scsi 0:0:0:0: ABORT operation timed-out. scsi 0:0:0:0: DEVICE RESET operation started scsi 0:0:0:0: DEVICE RESET operation timed-out. scsi 0:0:0:0: BUS RESET operation started scsi 0:0:0:0: BUS RESET operation timed-out. scsi 0:0:0:0: HOST RESET operation started sym0: SCSI BUS has been reset ------------ Bisecting gives commit 1bc39ac5dab265b76ce6e20d6c85f900539fd190 ("ARM: PCI: versatile: fix PCI interrupt setup") -- specifically the change to use common swizzle instead of NULL. Further analysis shows that interrupt mapping is wrong for the versatile hardware. Thanks to Paul Gortmaker for bisecting the problem and finding an initial solution, to Russell King for providing the correct interrupt mapping, and to Peter Maydell for tracking down board information. Signed-off-by: Guenter Roeck --- arch/arm/mach-versatile/pci.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c index e92e5e0..f435267 100644 --- a/arch/arm/mach-versatile/pci.c +++ b/arch/arm/mach-versatile/pci.c @@ -327,13 +327,13 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { int irq; - /* slot, pin, irq - * 24 1 IRQ_SIC_PCI0 - * 25 1 IRQ_SIC_PCI1 - * 26 1 IRQ_SIC_PCI2 - * 27 1 IRQ_SIC_PCI3 + /* + * Slot INTA INTB INTC INTD + * 31 PCI1 PCI2 PCI3 PCI0 + * 30 PCI0 PCI1 PCI2 PCI3 + * 29 PCI3 PCI0 PCI1 PCI2 */ - irq = IRQ_SIC_PCI0 + ((slot - 24 + pin - 1) & 3); + irq = IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3); return irq; }