From patchwork Mon Sep 2 21:31:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell King - ARM Linux X-Patchwork-Id: 2852970 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A36E79F3DC for ; Mon, 2 Sep 2013 21:32:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 843A52020A for ; Mon, 2 Sep 2013 21:32:11 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6813D20208 for ; Mon, 2 Sep 2013 21:32:10 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VGbjB-0005js-5l; Mon, 02 Sep 2013 21:32:05 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VGbj8-0008H8-VQ; Mon, 02 Sep 2013 21:32:02 +0000 Received: from [2002:4e20:1eda::1] (helo=caramon.arm.linux.org.uk) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VGbj5-0008GR-V6 for linux-arm-kernel@lists.infradead.org; Mon, 02 Sep 2013 21:32:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=caramon; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=GIYWjZitctEeFQor859VGciW3kvSYBBp8G0ZTkqhdO0=; b=dsbs77OYzzOtyPcao3/j8+eFbDbFKijMscjB27Cg2HPI9BpkiDXbJM0ZMFADLrW2vavOIKdh7vSau7rsKAsN2XW4PENr59vn6VsVYvMB50YD7LpcU0mG6UbZfR2j4ixoR9gXizikgl93pq9MhJBGrLwBnL8MAgjB3jE8gb8nNI0=; Received: from n2100.arm.linux.org.uk ([2002:4e20:1eda:1:214:fdff:fe10:4f86]:45054) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1VGbia-0006Lh-0K; Mon, 02 Sep 2013 22:31:28 +0100 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.76) (envelope-from ) id 1VGbiY-0007HW-Jq; Mon, 02 Sep 2013 22:31:26 +0100 Date: Mon, 2 Sep 2013 22:31:25 +0100 From: Russell King - ARM Linux To: Rob Herring Subject: Re: [PATCH v4] ARM: Add check for Cortex-A15 errata 798181 ECO Message-ID: <20130902213125.GB6617@n2100.arm.linux.org.uk> References: <1377440747-4564-1-git-send-email-robherring2@gmail.com> <20130902135842.GU6617@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20130902135842.GU6617@n2100.arm.linux.org.uk> User-Agent: Mutt/1.5.19 (2009-01-05) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130902_173200_419900_BBB26251 X-CRM114-Status: GOOD ( 26.88 ) X-Spam-Score: -1.0 (-) Cc: Will Deacon , linux-arm-kernel@lists.infradead.org, Rob Herring X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Mon, Sep 02, 2013 at 02:58:42PM +0100, Russell King - ARM Linux wrote: > On Sun, Aug 25, 2013 at 09:25:47AM -0500, Rob Herring wrote: > > From: Rob Herring > > > > The work-around for A15 errata 798181 is not needed if appropriate ECO > > fixes have been applied to r3p2 and earlier core revisions. This can be > > checked by reading REVIDR register bits 4 and 9. If only bit 4 is set, > > then the IPI broadcast can be skipped. > > > > Signed-off-by: Rob Herring > > So, this patch in the patch system claims to be against v3.11-rc2: > > $ git checkout v3.11-rc2 > ... > $ pdb gitapply 7804/2 > Patching 7804/2... > git apply --whitespace=fix -p1 --index --check > /tmp/pdb.15757 2>&1 exited with non-zero status: 256 > error: patch failed: arch/arm/include/asm/tlbflush.h:443 > error: arch/arm/include/asm/tlbflush.h: patch does not apply > error: patch failed: arch/arm/kernel/smp_tlb.c:70 > error: arch/arm/kernel/smp_tlb.c: patch does not apply > error: patch failed: arch/arm/mm/context.c:245 > error: arch/arm/mm/context.c: patch does not apply > > > v3: > > - Rebase to v3.11-rc5 due to commit 1f49856 (ARM: 7789/1: Do not run > > dummy_flush_tlb_a15_erratum() on non-Cortex-A15) > > - Move the revision checking out of line and use function ptrs. > > Hmm, so -rc5 not -rc2 that you put into the patch system... Also, the > patch you put into the patch system didn't have Will's ack on it. And... merging everything together tonight gives me a conflict with Will's barriers patches, which I've resolved like this - this will need to be checked: diff --cc arch/arm/include/asm/tlbflush.h index decff8d,3896026..0000000 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@@ -434,25 -545,51 +545,31 @@@ static inline void local_flush_bp_all(v const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; + __local_flush_bp_all(); if (tlb_flag(TLB_V7_UIS_BP)) - asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); - else if (tlb_flag(TLB_V6_BP)) asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); + } - if (tlb_flag(TLB_BARRIER)) - isb(); + static inline void __flush_bp_all(void) + { + const int zero = 0; + const unsigned int __tlb_flag = __cpu_tlb_flags; + + __local_flush_bp_all(); + if (tlb_flag(TLB_V7_UIS_BP)) + asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); } -#include -#ifdef CONFIG_ARM_ERRATA_798181 -static inline int erratum_a15_798181(void) -{ - unsigned int midr = read_cpuid_id(); - - /* Cortex-A15 r0p0..r3p2 affected */ - if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2) - return 0; - return 1; -} - -static inline void dummy_flush_tlb_a15_erratum(void) -{ - /* - * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0. - */ - asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); - dsb(ish); -} -#else -static inline int erratum_a15_798181(void) -{ - return 0; -} +extern void erratum_a15_798181_init(void); +extern bool (*erratum_a15_798181_handler)(void); -static inline void dummy_flush_tlb_a15_erratum(void) +static inline bool erratum_a15_798181(void) { + if (unlikely(IS_ENABLED(CONFIG_ARM_ERRATA_798181) && + erratum_a15_798181_handler)) + return erratum_a15_798181_handler(); + return false; } -#endif /* * flush_pmd_entry diff --cc arch/arm/mm/context.c index 28daa1c,84e6f77..0000000 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c index 12ab803..3bb055d 100644 --- a/arch/arm/kernel/smp_tlb.c +++ b/arch/arm/kernel/smp_tlb.c @@ -75,14 +75,14 @@ bool (*erratum_a15_798181_handler)(void); static bool erratum_a15_798181_partial(void) { asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); - dsb(); + dsb(ish); return false; } static bool erratum_a15_798181_broadcast(void) { asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); - dsb(); + dsb(ish); return true; }