===================================================================
@@ -0,0 +1,21 @@
+Broadcom BCM4760 System Timer device tree bindings
+--------------------------------------------------
+
+The BCM4760 Timer peripheral provides either two or four 32-bit timer
+channels. Three timer blocks are available at 0xba000, 0xbb000 and
+0xd1000. The first two provide four channels, the last (in the AON -
+Always ON power domain) provides only two.
+
+Required properties:
+
+- compatible : should be "brcm,bcm4760-system-timer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 2 or 4 interrupt sinks; one per timer channel.
+
+Example:
+
+timer@ba000 {
+ compatible = "brcm,bcm4760-system-timer";
+ reg = <0xba000 0x1000>;
+ interrupts = <4>, <11>;
+};
===================================================================
@@ -27,6 +27,13 @@
#size-cells = <1>;
ranges;
+ timer@ba000 {
+ compatible = "brcm,bcm4760-system-timer";
+ reg = <0xba000 0x1000>;
+ interrupt-parent = <&vic0>;
+ interrupts = <4>, <11>;
+ };
+
vic0: interrupt-controller@80000 {
compatible = "brcm,bcm4760-pl192", "arm,pl192-vic", "arm,primecell";
reg = <0x80000 0x1000>;
===================================================================
@@ -17,6 +17,7 @@ obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clk
obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
obj-$(CONFIG_ORION_TIMER) += time-orion.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
+obj-$(CONFIG_ARCH_BCM4760) += bcm4760_timer.o
obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o
obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
===================================================================
@@ -0,0 +1,147 @@
+/*
+ * Broadcom BCM4760 based ARM11 SoCs system timer
+ *
+ * Copyright (C) 2012 Domenico Andreoli <domenico.andreoli@linux.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#define TIMER_LOAD_OFFSET 0x00 /* load */
+#define TIMER_VALUE_OFFSET 0x04 /* value */
+#define TIMER_CONTROL_OFFSET 0x08 /* control */
+#define TIMER_INTCLR_OFFSET 0x0c /* interrupt clear */
+#define TIMER_RIS_OFFSET 0x10 /* raw interrupt */
+#define TIMER_MIS_OFFSET 0x14 /* masked interrupt status */
+#define TIMER_BGLOAD_OFFSET 0x18 /* background load */
+
+#define TIMER_CTRL_ONESHOTMODE BIT(0) /* One shot mode */
+#define TIMER_CTRL_32BIT BIT(1) /* 32-bit counter mode */
+#define TIMER_CTRL_IE BIT(5) /* Interrupt enable */
+#define TIMER_CTRL_PERIODIC BIT(6) /* Periodic mode */
+#define TIMER_CTRL_EN BIT(7) /* Timer enable */
+#define TIMER_CTRL_CLK2 BIT(9) /* Clock 2 selected */
+#define TIMER_CTRL_PREBY16 (1 << 2) /* prescale divide by 16 */
+#define TIMER_CTRL_PREBY256 (2 << 2) /* prescale divide by 256 */
+
+struct bcm4760_timer {
+ void __iomem *base;
+ struct clock_event_device evt;
+ struct irqaction act;
+};
+
+static inline u32 bcm4760_readl(struct bcm4760_timer *timer, unsigned long reg)
+{
+ return readl(timer->base + reg);
+}
+
+static inline void bcm4760_writel(struct bcm4760_timer *timer, unsigned long reg, u32 val)
+{
+ writel(val, timer->base + reg);
+}
+
+static void bcm4760_timer_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt_dev)
+{
+ struct bcm4760_timer *timer;
+ u32 val;
+
+ timer = container_of(evt_dev, struct bcm4760_timer, evt);
+ val = TIMER_CTRL_CLK2 | TIMER_CTRL_32BIT |
+ TIMER_CTRL_IE | TIMER_CTRL_EN;
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_ONESHOT:
+ bcm4760_writel(timer, TIMER_CONTROL_OFFSET, val | TIMER_CTRL_ONESHOTMODE);
+ break;
+ case CLOCK_EVT_MODE_RESUME:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ break;
+ default:
+ WARN(1, "%s: unhandled event mode %d\n", __func__, mode);
+ break;
+ }
+}
+
+static int bcm4760_timer_set_next_event(unsigned long event,
+ struct clock_event_device *evt_dev)
+{
+ struct bcm4760_timer *timer;
+
+ timer = container_of(evt_dev, struct bcm4760_timer, evt);
+ bcm4760_writel(timer, TIMER_LOAD_OFFSET, event);
+
+ return 0;
+}
+
+static irqreturn_t bcm4760_timer_interrupt(int irq, void *dev_id)
+{
+ struct bcm4760_timer *timer = dev_id;
+
+ /* check the (masked) interrupt status */
+ if (!bcm4760_readl(timer, TIMER_MIS_OFFSET))
+ return IRQ_NONE;
+
+ /* clear the timer interrupt */
+ bcm4760_writel(timer, TIMER_INTCLR_OFFSET, 1);
+
+ timer->evt.event_handler(&timer->evt);
+ return IRQ_HANDLED;
+}
+
+static void __init bcm4760_init_time(struct device_node *node)
+{
+ void __iomem *base;
+ u32 freq = 24000000;
+ int irq;
+ struct bcm4760_timer *timer;
+
+ base = of_iomap(node, 0);
+ if (!base)
+ panic("Can't remap timer registers");
+
+ timer = kzalloc(sizeof(*timer), GFP_KERNEL);
+ if (!timer)
+ panic("Can't allocate timer struct\n");
+
+ irq = irq_of_parse_and_map(node, 0);
+ if (irq <= 0)
+ panic("Can't parse timer IRQ");
+
+ timer->base = base;
+
+ timer->evt.name = node->name;
+ timer->evt.rating = 300;
+ timer->evt.features = CLOCK_EVT_FEAT_ONESHOT;
+ timer->evt.set_mode = bcm4760_timer_set_mode;
+ timer->evt.set_next_event = bcm4760_timer_set_next_event;
+ timer->evt.cpumask = cpumask_of(0);
+
+ clockevents_config_and_register(&timer->evt, freq, 0xf, 0xffffffff);
+
+ timer->act.name = node->name;
+ timer->act.flags = IRQF_TIMER | IRQF_SHARED;
+ timer->act.dev_id = timer;
+ timer->act.handler = bcm4760_timer_interrupt;
+
+ if (setup_irq(irq, &timer->act))
+ panic("Can't set up timer IRQ\n");
+}
+
+CLOCKSOURCE_OF_DECLARE(bcm4760, "brcm,bcm4760-system-timer", bcm4760_init_time);
===================================================================
@@ -24,4 +24,5 @@ config ARCH_BCM4760
select ARM_AMBA
select ARM_VIC
select CLKSRC_OF
+ select GENERIC_CLOCKEVENTS
select SOC_BUS