From patchwork Sat Sep 14 15:20:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Domenico Andreoli X-Patchwork-Id: 2893491 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A7E119F1C0 for ; Sat, 14 Sep 2013 15:23:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7A4B120253 for ; Sat, 14 Sep 2013 15:23:37 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 25A6C20251 for ; Sat, 14 Sep 2013 15:23:36 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VKrgD-0007oG-B2; Sat, 14 Sep 2013 15:22:38 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VKrfy-0004uU-Gt; Sat, 14 Sep 2013 15:22:22 +0000 Received: from mail-ee0-x232.google.com ([2a00:1450:4013:c00::232]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VKrfS-0004qy-9c for linux-arm-kernel@lists.infradead.org; Sat, 14 Sep 2013 15:21:59 +0000 Received: by mail-ee0-f50.google.com with SMTP id d51so1141256eek.23 for ; Sat, 14 Sep 2013 08:21:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:user-agent:date:from:to:cc:subject:references :content-disposition; bh=I3vNnn2MiLOynxCciXBeFsEhM/GQtg5YOM5I2bkRF+c=; b=Y4fbZzacKlZad6UPkx7oi9yFmcy3J/cxkpTGmDCMEz1aYyLf0i8HvemJi7Uq0ymP+y G3avKt2q4h3OJv9qlCj/XeviKkX056PL+gfYE7AsylqWdkaqhH69f+UaZpOta9QfzibH R9P3BCBhKbgv3wOQj02t694tYmLf0grpVHpd75ids7Jy1yTp6tYQi8up0wVfdFGQ82O4 LvacFcuPs5FwNKQLvEr0bPDYzU5ZCTRnScnYbWudvmm8TO3XXKdPwa3kBbvTZzONI4ZE PitCB4+WbDaNKvF8y//p+mh+Q/RF/O2xokXmkw11jiWH1PBr4KumIlrRsoa5N2fbaOIq YHtw== X-Received: by 10.14.183.130 with SMTP id q2mr27220594eem.5.1379172088352; Sat, 14 Sep 2013 08:21:28 -0700 (PDT) Received: from shock.dandreoli.com (j115181.upc-j.chello.nl. [24.132.115.181]) by mx.google.com with ESMTPSA id m54sm24936651eex.2.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 14 Sep 2013 08:21:27 -0700 (PDT) Received: by shock.dandreoli.com (Postfix, from userid 1000) id 0B02C3401EE; Sat, 14 Sep 2013 17:21:23 +0200 (CEST) Message-Id: <20130914152123.750345578@gmail.com> User-Agent: quilt/0.60-1 Date: Sat, 14 Sep 2013 17:20:34 +0200 From: Domenico Andreoli To: Russell King - ARM Linux , Olof Johansson , Arnd Bergmann Subject: [PATCH v4 2/4] ARM: bcm4760: Add system timer References: <20130914152032.401907974@gmail.com> Content-Disposition: inline; filename=arm-bcm476x-add-system-timer.patch X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130914_112150_613442_9ED3F457 X-CRM114-Status: GOOD ( 22.39 ) X-Spam-Score: -1.9 (-) Cc: Domenico Andreoli , Thomas Gleixner , John Stultz , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Domenico Andreoli System timer implementation for the BCM4760 based SoCs. v4: * added bcm4760_readl/writel helpers to the system driver code and removed (my) previous (naive) helpers * inverted the order of clockevents_config_and_register() and setup_irq() so to simplify the irq handler * drop the clock frequency option from the DT (left-over form v2) v3: * unchanged v2: * dropped clock-frequency property, its allowed value was anyway fixed to 24MHz and not clearly related to any known clock v1: * initial release Cc: John Stultz Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Acked-by: Olof Johansson Signed-off-by: Domenico Andreoli --- Documentation/devicetree/bindings/timer/brcm,bcm4760-system-timer.txt | 21 + arch/arm/boot/dts/bcm4760.dtsi | 7 + arch/arm/mach-bcm/Kconfig | 1 + drivers/clocksource/Makefile | 1 + drivers/clocksource/bcm4760_timer.c | 147 ++++++++++ 5 files changed, 177 insertions(+) Index: b/Documentation/devicetree/bindings/timer/brcm,bcm4760-system-timer.txt =================================================================== --- /dev/null +++ b/Documentation/devicetree/bindings/timer/brcm,bcm4760-system-timer.txt @@ -0,0 +1,21 @@ +Broadcom BCM4760 System Timer device tree bindings +-------------------------------------------------- + +The BCM4760 Timer peripheral provides either two or four 32-bit timer +channels. Three timer blocks are available at 0xba000, 0xbb000 and +0xd1000. The first two provide four channels, the last (in the AON - +Always ON power domain) provides only two. + +Required properties: + +- compatible : should be "brcm,bcm4760-system-timer" +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 2 or 4 interrupt sinks; one per timer channel. + +Example: + +timer@ba000 { + compatible = "brcm,bcm4760-system-timer"; + reg = <0xba000 0x1000>; + interrupts = <4>, <11>; +}; Index: b/arch/arm/boot/dts/bcm4760.dtsi =================================================================== --- a/arch/arm/boot/dts/bcm4760.dtsi +++ b/arch/arm/boot/dts/bcm4760.dtsi @@ -27,6 +27,13 @@ #size-cells = <1>; ranges; + timer@ba000 { + compatible = "brcm,bcm4760-system-timer"; + reg = <0xba000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <4>, <11>; + }; + vic0: interrupt-controller@80000 { compatible = "brcm,bcm4760-pl192", "arm,pl192-vic", "arm,primecell"; reg = <0x80000 0x1000>; Index: b/drivers/clocksource/Makefile =================================================================== --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clk obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o obj-$(CONFIG_ORION_TIMER) += time-orion.o obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o +obj-$(CONFIG_ARCH_BCM4760) += bcm4760_timer.o obj-$(CONFIG_ARCH_MARCO) += timer-marco.o obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o obj-$(CONFIG_ARCH_MXS) += mxs_timer.o Index: b/drivers/clocksource/bcm4760_timer.c =================================================================== --- /dev/null +++ b/drivers/clocksource/bcm4760_timer.c @@ -0,0 +1,147 @@ +/* + * Broadcom BCM4760 based ARM11 SoCs system timer + * + * Copyright (C) 2012 Domenico Andreoli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER_LOAD_OFFSET 0x00 /* load */ +#define TIMER_VALUE_OFFSET 0x04 /* value */ +#define TIMER_CONTROL_OFFSET 0x08 /* control */ +#define TIMER_INTCLR_OFFSET 0x0c /* interrupt clear */ +#define TIMER_RIS_OFFSET 0x10 /* raw interrupt */ +#define TIMER_MIS_OFFSET 0x14 /* masked interrupt status */ +#define TIMER_BGLOAD_OFFSET 0x18 /* background load */ + +#define TIMER_CTRL_ONESHOTMODE BIT(0) /* One shot mode */ +#define TIMER_CTRL_32BIT BIT(1) /* 32-bit counter mode */ +#define TIMER_CTRL_IE BIT(5) /* Interrupt enable */ +#define TIMER_CTRL_PERIODIC BIT(6) /* Periodic mode */ +#define TIMER_CTRL_EN BIT(7) /* Timer enable */ +#define TIMER_CTRL_CLK2 BIT(9) /* Clock 2 selected */ +#define TIMER_CTRL_PREBY16 (1 << 2) /* prescale divide by 16 */ +#define TIMER_CTRL_PREBY256 (2 << 2) /* prescale divide by 256 */ + +struct bcm4760_timer { + void __iomem *base; + struct clock_event_device evt; + struct irqaction act; +}; + +static inline u32 bcm4760_readl(struct bcm4760_timer *timer, unsigned long reg) +{ + return readl(timer->base + reg); +} + +static inline void bcm4760_writel(struct bcm4760_timer *timer, unsigned long reg, u32 val) +{ + writel(val, timer->base + reg); +} + +static void bcm4760_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt_dev) +{ + struct bcm4760_timer *timer; + u32 val; + + timer = container_of(evt_dev, struct bcm4760_timer, evt); + val = TIMER_CTRL_CLK2 | TIMER_CTRL_32BIT | + TIMER_CTRL_IE | TIMER_CTRL_EN; + + switch (mode) { + case CLOCK_EVT_MODE_ONESHOT: + bcm4760_writel(timer, TIMER_CONTROL_OFFSET, val | TIMER_CTRL_ONESHOTMODE); + break; + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_SHUTDOWN: + break; + default: + WARN(1, "%s: unhandled event mode %d\n", __func__, mode); + break; + } +} + +static int bcm4760_timer_set_next_event(unsigned long event, + struct clock_event_device *evt_dev) +{ + struct bcm4760_timer *timer; + + timer = container_of(evt_dev, struct bcm4760_timer, evt); + bcm4760_writel(timer, TIMER_LOAD_OFFSET, event); + + return 0; +} + +static irqreturn_t bcm4760_timer_interrupt(int irq, void *dev_id) +{ + struct bcm4760_timer *timer = dev_id; + + /* check the (masked) interrupt status */ + if (!bcm4760_readl(timer, TIMER_MIS_OFFSET)) + return IRQ_NONE; + + /* clear the timer interrupt */ + bcm4760_writel(timer, TIMER_INTCLR_OFFSET, 1); + + timer->evt.event_handler(&timer->evt); + return IRQ_HANDLED; +} + +static void __init bcm4760_init_time(struct device_node *node) +{ + void __iomem *base; + u32 freq = 24000000; + int irq; + struct bcm4760_timer *timer; + + base = of_iomap(node, 0); + if (!base) + panic("Can't remap timer registers"); + + timer = kzalloc(sizeof(*timer), GFP_KERNEL); + if (!timer) + panic("Can't allocate timer struct\n"); + + irq = irq_of_parse_and_map(node, 0); + if (irq <= 0) + panic("Can't parse timer IRQ"); + + timer->base = base; + + timer->evt.name = node->name; + timer->evt.rating = 300; + timer->evt.features = CLOCK_EVT_FEAT_ONESHOT; + timer->evt.set_mode = bcm4760_timer_set_mode; + timer->evt.set_next_event = bcm4760_timer_set_next_event; + timer->evt.cpumask = cpumask_of(0); + + clockevents_config_and_register(&timer->evt, freq, 0xf, 0xffffffff); + + timer->act.name = node->name; + timer->act.flags = IRQF_TIMER | IRQF_SHARED; + timer->act.dev_id = timer; + timer->act.handler = bcm4760_timer_interrupt; + + if (setup_irq(irq, &timer->act)) + panic("Can't set up timer IRQ\n"); +} + +CLOCKSOURCE_OF_DECLARE(bcm4760, "brcm,bcm4760-system-timer", bcm4760_init_time); Index: b/arch/arm/mach-bcm/Kconfig =================================================================== --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -24,4 +24,5 @@ config ARCH_BCM4760 select ARM_AMBA select ARM_VIC select CLKSRC_OF + select GENERIC_CLOCKEVENTS select SOC_BUS