From patchwork Fri Dec 6 15:17:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Grzeschik X-Patchwork-Id: 3298691 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 02948C0D4A for ; Fri, 6 Dec 2013 15:18:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D2AD520454 for ; Fri, 6 Dec 2013 15:18:17 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 15F5C2042A for ; Fri, 6 Dec 2013 15:18:16 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VoxAK-0007AD-7t; Fri, 06 Dec 2013 15:18:04 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VoxAH-0000aK-LQ; Fri, 06 Dec 2013 15:18:01 +0000 Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VoxAE-0000ZQ-QP for linux-arm-kernel@lists.infradead.org; Fri, 06 Dec 2013 15:17:59 +0000 Received: from ptx.hi.pengutronix.de ([2001:6f8:1178:2:5054:ff:fec0:8e10] ident=Debian-exim) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1Vox9s-00074K-Q0; Fri, 06 Dec 2013 16:17:36 +0100 Received: from mgr by ptx.hi.pengutronix.de with local (Exim 4.80) (envelope-from ) id 1Vox9p-0001r8-Ut; Fri, 06 Dec 2013 16:17:33 +0100 Date: Fri, 6 Dec 2013 16:17:33 +0100 From: Michael Grzeschik To: Peter Chen Subject: Re: [PATCH 2/4 V2] ARM: mx28: Add USB PHY overcurrent pinmux Message-ID: <20131206151733.GD2374@pengutronix.de> References: <1345852300-2213-1-git-send-email-marex@denx.de> <1345852300-2213-2-git-send-email-marex@denx.de> <20131122154947.GE24508@pengutronix.de> <201311250058.32881.marex@denx.de> <20131125134248.GA28906@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-IRC: #ptxdist @freenode X-Accept-Language: de,en X-Accept-Content-Type: text/plain X-Uptime: 16:12:44 up 104 days, 43 min, 54 users, load average: 0, 04, 0, 09, 0,31 User-Agent: Mutt/1.5.21 (2010-09-15) X-SA-Exim-Connect-IP: 2001:6f8:1178:2:5054:ff:fec0:8e10 X-SA-Exim-Mail-From: mgr@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131206_101759_359507_57E5F36F X-CRM114-Status: GOOD ( 26.60 ) X-Spam-Score: -2.1 (--) Cc: Marek Vasut , Fabio Estevam , Shawn Guo , Mark Brown , "linux-usb@vger.kernel.org" , Chris Ball , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Peter, On Tue, Nov 26, 2013 at 12:08:03PM +0000, Peter Chen wrote: > > The GPIO is working for this pin. But also the DIGCTL register bits > > helped here. Now the OC event triggers if the pin gets pulled to 3V3. > > > > I am currently looking for a good place to enable the DIGCTL bits. > > I suggest to enable them per default. As we don't have USBMISC registers > > in MX28, the bits should be toggled in ci_hdrc_imx.c if the of property > > "disable-overcurrent" is not found. I will use the syscon interface to > > reach them with the regmap interface. > > > usbmisc register doesn't stand for the register needs to be in usb controller. > Any registers which are related to USB function can be considered as usbmisc > registers. You will see FSL-style SoC, the over-current or other related setting > are at controller base + 0x800 (0x600), but Sigmatel-style SoC (mx28/mx23), the usb > register are not at controller register region. > > My suggestion is: create usbmisc node for mx28, and put oc setting at there, it can > keep ci_hdrc_imx.c clean. > Besides, you may need two dts user setting for oc enable and oc polarity. IMHO usbmisc is a driver with memery mapped region. So it would probably make more sense to use syscon for that purpose, as we only need special registers out of the digctl register. What do you think of that code: Thanks, Michael diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c b/drivers/usb/chipidea/ci_hdrc_imx.c index 68f7f5e..ddac5cb 100644 --- a/drivers/usb/chipidea/ci_hdrc_imx.c +++ b/drivers/usb/chipidea/ci_hdrc_imx.c @@ -19,12 +19,18 @@ #include #include #include +#include +#include #include "ci.h" #include "ci_hdrc_imx.h" #define CI_HDRC_IMX_IMX28_WRITE_FIX BIT(0) +#define DIGCTL_CTRL_SET 0x4 +#define USB_OTG_OC_ENABLE_BIT BIT(23) +#define USB_H1_OC_ENABLE_BIT BIT(24) + struct ci_hdrc_imx_platform_flag { unsigned int flags; }; @@ -105,6 +111,26 @@ static int ci_hdrc_imx_probe(struct platform_device *pdev) const struct of_device_id *of_id = of_match_device(ci_hdrc_imx_dt_ids, &pdev->dev); const struct ci_hdrc_imx_platform_flag *imx_platform_flag = of_id->data; + struct device_node *np = pdev->dev.of_node; + struct regmap *digctl; + + /* Some SoCs don't have digctl registers */ + if (of_get_property(np, "fsl,digctl", NULL)) { + struct of_phandle_args args; + int enable_bit = USB_OTG_OC_ENABLE_BIT; + ret = of_parse_phandle_with_args(np, "fsl,digctl", "#index-cells", + 0, &args); + digctl = syscon_regmap_lookup_by_phandle + (np, "fsl,digctl"); + if (IS_ERR(digctl)) { + dev_dbg(&pdev->dev, + "failed to find regmap for digctl\n"); + } else { + if (args.args[0]) + enable_bit = USB_H1_OC_ENABLE_BIT; + regmap_write(digctl, DIGCTL_CTRL_SET, enable_bit); + } + } data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); if (!data) { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 600f7cb..bb61c49 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -668,11 +668,12 @@ }; }; - digctl@8001c000 { - compatible = "fsl,imx28-digctl"; + digctl: digctl@8001c000 { + #index-cells = <1>; + compatible = "fsl,imx28-digctl", "syscon"; reg = <0x8001c000 0x2000>; interrupts = <89>; - status = "disabled"; + status = "okay"; }; etm@80022000 { @@ -976,6 +977,7 @@ interrupts = <93>; clocks = <&clks 60>; fsl,usbphy = <&usbphy0>; + fsl,digctl = <&digctl 0>; status = "disabled"; }; @@ -985,6 +987,7 @@ interrupts = <92>; clocks = <&clks 61>; fsl,usbphy = <&usbphy1>; + fsl,digctl = <&digctl 1>; status = "disabled"; };