From patchwork Thu Jan 16 07:36:56 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 3497411 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 69B4CC02DC for ; Thu, 16 Jan 2014 07:35:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3DFDD2017D for ; Thu, 16 Jan 2014 07:35:56 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B45D2017B for ; Thu, 16 Jan 2014 07:35:54 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W3hUT-0002DQ-Do; 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Thu, 16 Jan 2014 07:35:19 +0000 (UTC) Received: from VA3EHSMHS040.bigfish.com (unknown [10.7.14.228]) by mail6-va3.bigfish.com (Postfix) with ESMTP id 2C68D2004B; Thu, 16 Jan 2014 07:35:19 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS040.bigfish.com (10.7.99.50) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 16 Jan 2014 07:35:19 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.158.2; Thu, 16 Jan 2014 07:35:18 +0000 Received: from S2101-09.ap.freescale.net ([10.192.185.143]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s0G7ZEbj002338; Thu, 16 Jan 2014 00:35:15 -0700 Date: Thu, 16 Jan 2014 15:36:56 +0800 From: Shawn Guo To: Anson Huang Subject: Re: [PATCH V6 3/3] ARM: imx: add suspend in ocram support for i.mx6sl Message-ID: <20140116073655.GC4049@S2101-09.ap.freescale.net> References: <1389840105-17625-1-git-send-email-b20788@freescale.com> <1389840105-17625-3-git-send-email-b20788@freescale.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1389840105-17625-3-git-send-email-b20788@freescale.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: sigmatel.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140116_023544_184625_F31C940A X-CRM114-Status: GOOD ( 12.37 ) X-Spam-Score: -2.3 (--) Cc: linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD,UNPARSEABLE_RELAY,UNRESOLVED_TEMPLATE autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, Jan 16, 2014 at 10:41:45AM +0800, Anson Huang wrote: > @@ -119,6 +120,31 @@ > > .endm > > + .macro reset_mmdc_read_fifo > + > + /* reset read FIFO, RST_RD_FIFO */ > + ldr r7, =MX6Q_MMDC_MPDGCTRL0 > + ldr r6, [r11, r7] > + orr r6, r6, #(1 << 31) > + str r6, [r11, r7] > +1: > + ldr r6, [r11, r7] > + and r6, r6, #(1 << 31) > + cmp r6, #0 Use 'ands' to save the 'cmp'. > + bne 1b > + > + /* reset FIFO a second time */ > + ldr r6, [r11, r7] > + orr r6, r6, #(1 << 31) > + str r6, [r11, r7] > +2: > + ldr r6, [r11, r7] > + and r6, r6, #(1 << 31) > + cmp r6, #0 Ditto > + bne 2b > + > + .endm > + > ENTRY(imx6_suspend) > ldr r1, [r0, #PM_INFO_PBASE_OFFSET] > ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] > @@ -286,6 +335,14 @@ resume: > restore_mmdc_io > > ldr r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] > + > + ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET] > + cmp r3, #MXC_CPU_IMX6SL > + bne dsm_restore_mmdc_io_done > + > + reset_mmdc_read_fifo > +dsm_restore_mmdc_io_done: > + > enable_mmdc_access > > mov pc, lr Instead of creating 3 macros, restore_mmdc_io, reset_mmdc_read_fifo and enable_mmdc_access, I was actually suggesting to do all the mmdc resume work in one macro. We will need to tell the macro whether we're running at virtual or physical space. For you reference, the following changes are what I made on top of yours. Shawn ---8<------- diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S index 570fede..1ba8fc8 100644 --- a/arch/arm/mach-imx/suspend-imx6.S +++ b/arch/arm/mach-imx/suspend-imx6.S @@ -18,8 +18,8 @@ * * Better to follow below rules to use ARM registers: * r0: pm_info structure address; - * r1 ~ r5: for saving pm_info members; - * r6 ~ r10: free registers; + * r1 ~ r4: for saving pm_info members; + * r5 ~ r10: free registers; * r11: io base address. * * suspend ocram space layout: @@ -87,9 +87,13 @@ .endm - .macro restore_mmdc_io + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0 + ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] - /* r11 must be the MMDC IO address before calling it */ ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET add r7, r7, r0 @@ -100,48 +104,45 @@ subs r6, r6, #0x1 bne 1b - .endm - - .macro enable_mmdc_access + cmp r5, #0 + ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] - /* let DDR out of self-refresh */ - ldr r7, [r11, #MX6Q_MMDC_MAPSR] - bic r7, r7, #(1 << 21) - str r7, [r11, #MX6Q_MMDC_MAPSR] - -1: - ldr r7, [r11, #MX6Q_MMDC_MAPSR] - ands r7, r7, #(1 << 25) - bne 1b - /* enable DDR auto power saving */ - ldr r7, [r11, #MX6Q_MMDC_MAPSR] - bic r7, r7, #0x1 - str r7, [r11, #MX6Q_MMDC_MAPSR] - - .endm - - .macro reset_mmdc_read_fifo + cmp r3, #MXC_CPU_IMX6SL + bne 4f /* reset read FIFO, RST_RD_FIFO */ ldr r7, =MX6Q_MMDC_MPDGCTRL0 ldr r6, [r11, r7] orr r6, r6, #(1 << 31) str r6, [r11, r7] -1: +2: ldr r6, [r11, r7] - and r6, r6, #(1 << 31) - cmp r6, #0 - bne 1b + ands r6, r6, #(1 << 31) + bne 2b /* reset FIFO a second time */ ldr r6, [r11, r7] orr r6, r6, #(1 << 31) str r6, [r11, r7] -2: +3: ldr r6, [r11, r7] - and r6, r6, #(1 << 31) - cmp r6, #0 - bne 2b + ands r6, r6, #(1 << 31) + bne 3b + +4: + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r11, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 5b + /* enable DDR auto power saving */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r11, #MX6Q_MMDC_MAPSR] .endm @@ -281,8 +282,7 @@ set_mmdc_io_lpm_done: */ ldr r6, =2000 rbc_loop: - sub r6, r6, #0x1 - cmp r6, #0x0 + subs r6, r6, #0x1 bne rbc_loop /* Zzz, enter stop mode */ @@ -297,18 +297,8 @@ rbc_loop: * wakeup source, system should auto * resume, we need to restore MMDC IO first */ - ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] - restore_mmdc_io - - ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] - - cmp r3, #MXC_CPU_IMX6SL - bne restore_mmdc_io_done - - reset_mmdc_read_fifo -restore_mmdc_io_done: - - enable_mmdc_access + mov r5, #0 + resume_mmdc /* return to suspend finish */ mov pc, lr @@ -331,19 +321,9 @@ resume: str r7, [r11, #MX6Q_SRC_GPR1] str r7, [r11, #MX6Q_SRC_GPR2] - ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] - restore_mmdc_io - - ldr r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] - ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET] - cmp r3, #MXC_CPU_IMX6SL - bne dsm_restore_mmdc_io_done - - reset_mmdc_read_fifo -dsm_restore_mmdc_io_done: - - enable_mmdc_access + mov r5, #1 + resume_mmdc mov pc, lr ENDPROC(imx6_suspend)