From patchwork Wed Feb 5 13:53:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?David_Lanzend=C3=B6rfer?= X-Patchwork-Id: 3586391 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8800CC02DC for ; Wed, 5 Feb 2014 13:56:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B36C720121 for ; Wed, 5 Feb 2014 13:56:27 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E21A520181 for ; Wed, 5 Feb 2014 13:56:22 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WB2wJ-00018B-HK; Wed, 05 Feb 2014 13:54:56 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WB2vt-0003Sk-Q0; Wed, 05 Feb 2014 13:54:29 +0000 Received: from kolab.o2s.ch ([2001:1620:2081::4]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WB2vs-0003R3-0E for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2014 13:54:28 +0000 Received: from localhost (localhost [127.0.0.1]) by kolab.o2s.ch (Postfix) with ESMTP id 255D4765CE; Wed, 5 Feb 2014 14:57:21 +0100 (CET) X-Virus-Scanned: amavisd-new at example.com Received: from kolab.o2s.ch ([127.0.0.1]) by localhost (kolab.o2s.ch [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RsgJkgFSwcwt; Wed, 5 Feb 2014 14:57:20 +0100 (CET) Received: from dizzy-6.o2s.ch (unknown [IPv6:2001:470:26:484:6ef0:49ff:fee6:8dca]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by kolab.o2s.ch (Postfix) with ESMTPSA id CE34D765BF; Wed, 5 Feb 2014 14:57:18 +0100 (CET) Subject: [PATCH v3 2/7] clk: sunxi: Implement MMC phase control To: devicetree@vger.kernel.org, Ulf Hansson , Laurent Pinchart , Simon Baatz , Hans de Goede , Emilio =?utf-8?b?TMOzcGV6?= , linux-mmc@vger.kernel.org, Chris Ball , linux-kernel@vger.kernel.org, H Hartley Sweeten , linux-sunxi@googlegroups.com, Tejun Heo , Maxime Ripard , Guennadi Liakhovetski , linux-arm-kernel@lists.infradead.org From: David =?utf-8?q?Lanzend=C3=B6rfer?= Date: Wed, 05 Feb 2014 14:53:59 +0100 Message-ID: <20140205135357.3027.39081.stgit@dizzy-6.o2s.ch> In-Reply-To: <20140205134741.3027.50207.stgit@dizzy-6.o2s.ch> References: <20140205134741.3027.50207.stgit@dizzy-6.o2s.ch> User-Agent: StGit/0.16 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140205_085428_174696_95D8D34C X-CRM114-Status: UNSURE ( 9.79 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Emilio López Signed-off-by: Emilio López --- drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index abb6c5a..33b9977 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -377,6 +377,41 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, /** + * clk_sunxi_mmc_phase_control() - configures MMC clock phase control + */ + +void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output) +{ + #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) + #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) + + struct clk_composite *composite = to_clk_composite(hw); + struct clk_hw *rate_hw = composite->rate_hw; + struct clk_factors *factors = to_clk_factors(rate_hw); + unsigned long flags = 0; + u32 reg; + + if (factors->lock) + spin_lock_irqsave(factors->lock, flags); + + reg = readl(factors->reg); + + /* set sample clock phase control */ + reg &= ~(0x7 << 20); + reg |= ((sample & 0x7) << 20); + + /* set output clock phase control */ + reg &= ~(0x7 << 8); + reg |= ((output & 0x7) << 8); + + writel(reg, factors->reg); + + if (factors->lock) + spin_unlock_irqrestore(factors->lock, flags); +} + + +/** * sunxi_factors_clk_setup() - Setup function for factor clocks */