From patchwork Fri Apr 11 11:25:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell King - ARM Linux X-Patchwork-Id: 3967951 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A54919F336 for ; Fri, 11 Apr 2014 11:27:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CA55D20819 for ; Fri, 11 Apr 2014 11:27:17 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CFB8E2080F for ; Fri, 11 Apr 2014 11:27:16 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYZbU-0001jd-RY; Fri, 11 Apr 2014 11:26:40 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYZbL-0002Cs-OZ; Fri, 11 Apr 2014 11:26:31 +0000 Received: from bombadil.infradead.org ([2001:1868:205::9]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYZb0-0002BU-UF for linux-arm-kernel@merlin.infradead.org; Fri, 11 Apr 2014 11:26:13 +0000 Received: from pandora.arm.linux.org.uk ([2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYZax-0004Ea-0d for linux-arm-kernel@lists.infradead.org; Fri, 11 Apr 2014 11:26:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=pandora; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=oAzHxbiNpu3BLdPV4f7LfUjo6dRVWF9qQJathg83t/4=; b=lYgrGNedFYFeum+r4fvindVavMEt1haADFKWkMR4MdAghJsBhzYfk0d3Gmr24nZc/Ed4LOLnbOzFOawlGN/98EdXlYUuT9K+tJRri2OliRY2M9zBw/ToTZsrwBXMNZyEB5E6azGxXuSPyek5S/KCJnIX3joPnXYSWUL8Xj+mmsM=; Received: from n2100.arm.linux.org.uk ([fd8f:7570:feb6:1:214:fdff:fe10:4f86]:44918) by pandora.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1WYZaP-0002pr-Ak; Fri, 11 Apr 2014 12:25:33 +0100 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.76) (envelope-from ) id 1WYZZt-0007hI-GO; Fri, 11 Apr 2014 12:25:01 +0100 Date: Fri, 11 Apr 2014 12:25:01 +0100 From: Russell King - ARM Linux To: Sekhar Nori Subject: Re: [PATCH v2 3/3] ARM: OMAP2+: AM43x: L2 cache support Message-ID: <20140411112500.GM27282@n2100.arm.linux.org.uk> References: <20140404101808.GG27282@n2100.arm.linux.org.uk> <53440D73.6060504@ti.com> <20140409162327.GH27282@n2100.arm.linux.org.uk> <534686DF.7070207@ti.com> <20140410120348.GK27282@n2100.arm.linux.org.uk> <53468B8E.9040604@ti.com> <53469C29.8050906@ti.com> <20140410134028.GL27282@n2100.arm.linux.org.uk> <53477EC5.5080400@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <53477EC5.5080400@ti.com> User-Agent: Mutt/1.5.19 (2009-01-05) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140411_042607_387727_94EE3E2B X-CRM114-Status: GOOD ( 20.65 ) X-Spam-Score: -0.7 (/) Cc: Tony Lindgren , Linux OMAP Mailing List , Linux ARM Mailing List X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Fri, Apr 11, 2014 at 11:03:57AM +0530, Sekhar Nori wrote: > Here is a revised patch which is just an extension of your patch > with L2C-220 case handled. I dont really have L2C-220 hardware so even > if you want to handle that at a later time, it would be perfectly okay > with me. This is what I came up with, which of course is very similar to yours. I think the only difference is that I'm allowing the state of the NS access bits to be preserved by the OMAP code, getting OMAP closer to the target of a ~0 mask. The only bits which are clear in the mask passed into the L2 code by OMAP now are: - L310_AUX_CTRL_INSTR_PREFETCH - L310_AUX_CTRL_DATA_PREFETCH - L310_AUX_CTRL_CACHE_REPLACE_RR - L2C_AUX_CTRL_SHARED_OVERRIDE - L2C_AUX_CTRL_PARITY_ENABLE It sounds like we can kill L310_AUX_CTRL_CACHE_REPLACE_RR as well since that's already set for us (and fwir is the power-on-reset default too.) arch/arm/mach-omap2/omap4-common.c | 4 +--- arch/arm/mm/cache-l2x0.c | 23 +++++++++++++++++++++-- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index c0f9a81a2d32..3b01c5223b11 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -213,8 +213,6 @@ static int __init omap_l2_cache_init(void) /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR | - L310_AUX_CTRL_NS_LOCKDOWN | - L310_AUX_CTRL_NS_INT_CTRL | L2C_AUX_CTRL_SHARED_OVERRIDE | L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH; @@ -223,7 +221,7 @@ static int __init omap_l2_cache_init(void) if (of_have_populated_dt()) l2x0_of_init(aux_ctrl, 0xc19fffff); else - l2x0_init(l2cache_base, aux_ctrl, 0xc19fffff); + l2x0_init(l2cache_base, aux_ctrl, 0xcd9fffff); return 0; } diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 98796b789eb9..5ec454d51a9f 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -502,11 +502,23 @@ static void l2c220_sync(void) raw_spin_unlock_irqrestore(&l2x0_lock, flags); } +static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock) +{ + /* + * Always enable non-secure access to the lockdown registers - + * we write to them as part of the L2C enable sequence so they + * need to be accessible. + */ + aux |= L220_AUX_CTRL_NS_LOCKDOWN; + + l2c_enable(base, aux, num_lock); +} + static const struct l2c_init_data l2c220_data = { .type = "L2C-220", .way_size_0 = SZ_8K, .num_lock = 1, - .enable = l2c_enable, + .enable = l2c220_enable, .save = l2c_save, .outer_cache = { .inv_range = l2c220_inv_range, @@ -776,6 +788,13 @@ static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis"); } + /* + * Always enable non-secure access to the lockdown registers - + * we write to them as part of the L2C enable sequence so they + * need to be accessible. + */ + aux |= L310_AUX_CTRL_NS_LOCKDOWN; + l2c_enable(base, aux, num_lock); if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) { @@ -1052,7 +1071,7 @@ static const struct l2c_init_data of_l2c220_data __initconst = { .way_size_0 = SZ_8K, .num_lock = 1, .of_parse = l2x0_of_parse, - .enable = l2c_enable, + .enable = l2c220_enable, .save = l2c_save, .outer_cache = { .inv_range = l2c220_inv_range,