From patchwork Tue May 20 07:59:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 4207751 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 76A409F23C for ; Tue, 20 May 2014 08:01:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 820B620304 for ; Tue, 20 May 2014 08:01:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C96BB201FA for ; Tue, 20 May 2014 08:01:07 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WmewM-0001rP-3f; Tue, 20 May 2014 07:58:26 +0000 Received: from mail-pd0-x231.google.com ([2607:f8b0:400e:c02::231]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WmewG-0001jH-HV for linux-arm-kernel@lists.infradead.org; Tue, 20 May 2014 07:58:22 +0000 Received: by mail-pd0-f177.google.com with SMTP id g10so86942pdj.22 for ; Tue, 20 May 2014 00:57:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=93BffRJQD4HjY3EbxxpGtuVX1nBZuJTjSiLWEqjcLDg=; b=LxKnQjezh3qcDs1VAZZfgVkShQ8MIHgWroB1O+Jo6q7St6MWKmX1URw8QzRsGZmhJo AqgzPgT9/mbiXXe9rmUUaZgHd2FAh55qOyOJWt0uksQXYATiyDCUW8/3BZwUEHjohiie TKjPvgRw6SMVQpGW2ZJVYY6vOMh+AjoLn23XTMB+fX9SjYEXs+C2JkG2SUCRoiifwHqZ ijOJNlMENdF4P62fYsnCxh0RUxjnl+jGJ3My3YY545/j/PFeOxgf1xDhzhNIXpkF5MnX 6PQz5chKcUU4mQRmjoat1D3hL4ja7kCwHW0CdKaeVg1eLorcw4qSyzBxPmRNfd52ZrWd ARtg== X-Received: by 10.68.186.33 with SMTP id fh1mr48696361pbc.140.1400572679579; Tue, 20 May 2014 00:57:59 -0700 (PDT) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by mx.google.com with ESMTPSA id nf5sm1652321pbc.77.2014.05.20.00.57.56 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 May 2014 00:57:58 -0700 (PDT) From: Magnus Damm To: olof@lixom.net Date: Tue, 20 May 2014 16:59:59 +0900 Message-Id: <20140520075959.13851.45143.sendpatchset@w520> In-Reply-To: <20140520075949.13851.42995.sendpatchset@w520> References: <20140520075949.13851.42995.sendpatchset@w520> Subject: [PATCH 01/08] ARM: shmobile: Move intc.h, cleanup sh_intc.h usage X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140520_005820_656155_AED499F4 X-CRM114-Status: GOOD ( 12.37 ) X-Spam-Score: -0.1 (/) Cc: horms@verge.net.au, Magnus Damm , linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Change location of intc.h so it can be used as #include "intc.h" instead of the old style #include . Also clean up some code to get rid of redundant #include . Signed-off-by: Magnus Damm --- arch/arm/mach-shmobile/board-mackerel.c | 1 arch/arm/mach-shmobile/include/mach/intc.h | 290 ---------------------------- arch/arm/mach-shmobile/intc-sh7372.c | 3 arch/arm/mach-shmobile/intc-sh73a0.c | 3 arch/arm/mach-shmobile/intc.h | 290 ++++++++++++++++++++++++++++ arch/arm/mach-shmobile/setup-sh7372.c | 1 arch/arm/mach-shmobile/setup-sh73a0.c | 1 7 files changed, 292 insertions(+), 297 deletions(-) --- 0001/arch/arm/mach-shmobile/board-mackerel.c +++ work/arch/arm/mach-shmobile/board-mackerel.c 2014-05-19 23:03:09.000000000 +0900 @@ -47,7 +47,6 @@ #include #include #include -#include #include #include #include --- 0001/arch/arm/mach-shmobile/include/mach/intc.h +++ /dev/null 2013-06-03 21:41:10.638032047 +0900 @@ -1,290 +0,0 @@ -#ifndef __ASM_MACH_INTC_H -#define __ASM_MACH_INTC_H -#include - -#define INTC_IRQ_PINS_ENUM_16L(p) \ - p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ - p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7, \ - p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ - p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 - -#define INTC_IRQ_PINS_ENUM_16H(p) \ - p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ - p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23, \ - p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ - p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 - -#define INTC_IRQ_PINS_VECT_16L(p, vect) \ - vect(p ## _IRQ0, 0x0200), vect(p ## _IRQ1, 0x0220), \ - vect(p ## _IRQ2, 0x0240), vect(p ## _IRQ3, 0x0260), \ - vect(p ## _IRQ4, 0x0280), vect(p ## _IRQ5, 0x02a0), \ - vect(p ## _IRQ6, 0x02c0), vect(p ## _IRQ7, 0x02e0), \ - vect(p ## _IRQ8, 0x0300), vect(p ## _IRQ9, 0x0320), \ - vect(p ## _IRQ10, 0x0340), vect(p ## _IRQ11, 0x0360), \ - vect(p ## _IRQ12, 0x0380), vect(p ## _IRQ13, 0x03a0), \ - vect(p ## _IRQ14, 0x03c0), vect(p ## _IRQ15, 0x03e0) - -#define INTC_IRQ_PINS_VECT_16H(p, vect) \ - vect(p ## _IRQ16, 0x3200), vect(p ## _IRQ17, 0x3220), \ - vect(p ## _IRQ18, 0x3240), vect(p ## _IRQ19, 0x3260), \ - vect(p ## _IRQ20, 0x3280), vect(p ## _IRQ21, 0x32a0), \ - vect(p ## _IRQ22, 0x32c0), vect(p ## _IRQ23, 0x32e0), \ - vect(p ## _IRQ24, 0x3300), vect(p ## _IRQ25, 0x3320), \ - vect(p ## _IRQ26, 0x3340), vect(p ## _IRQ27, 0x3360), \ - vect(p ## _IRQ28, 0x3380), vect(p ## _IRQ29, 0x33a0), \ - vect(p ## _IRQ30, 0x33c0), vect(p ## _IRQ31, 0x33e0) - -#define INTC_IRQ_PINS_MASK_16L(p, base) \ - { base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A */ \ - { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ - p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ - { base + 0x44, base + 0x64, 8, /* INTMSK10A / INTMSKCLR10A */ \ - { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ - p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } - -#define INTC_IRQ_PINS_MASK_16H(p, base) \ - { base + 0x48, base + 0x68, 8, /* INTMSK20A / INTMSKCLR20A */ \ - { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ - p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ - { base + 0x4c, base + 0x6c, 8, /* INTMSK30A / INTMSKCLR30A */ \ - { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ - p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } - -#define INTC_IRQ_PINS_PRIO_16L(p, base) \ - { base + 0x10, 0, 32, 4, /* INTPRI00A */ \ - { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ - p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ - { base + 0x14, 0, 32, 4, /* INTPRI10A */ \ - { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ - p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } - -#define INTC_IRQ_PINS_PRIO_16H(p, base) \ - { base + 0x18, 0, 32, 4, /* INTPRI20A */ \ - { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ - p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ - { base + 0x1c, 0, 32, 4, /* INTPRI30A */ \ - { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ - p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } - -#define INTC_IRQ_PINS_SENSE_16L(p, base) \ - { base + 0x00, 32, 4, /* ICR1A */ \ - { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ - p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ - { base + 0x04, 32, 4, /* ICR2A */ \ - { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ - p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } - -#define INTC_IRQ_PINS_SENSE_16H(p, base) \ - { base + 0x08, 32, 4, /* ICR3A */ \ - { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ - p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ - { base + 0x0c, 32, 4, /* ICR4A */ \ - { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ - p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } - -#define INTC_IRQ_PINS_ACK_16L(p, base) \ - { base + 0x20, 0, 8, /* INTREQ00A */ \ - { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ - p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ - { base + 0x24, 0, 8, /* INTREQ10A */ \ - { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ - p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } - -#define INTC_IRQ_PINS_ACK_16H(p, base) \ - { base + 0x28, 0, 8, /* INTREQ20A */ \ - { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ - p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ - { base + 0x2c, 0, 8, /* INTREQ30A */ \ - { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ - p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } - -#define INTC_IRQ_PINS_16(p, base, vect, str) \ - \ -static struct resource p ## _resources[] __initdata = { \ - [0] = { \ - .start = base, \ - .end = base + 0x64, \ - .flags = IORESOURCE_MEM, \ - }, \ -}; \ - \ -enum { \ - p ## _UNUSED = 0, \ - INTC_IRQ_PINS_ENUM_16L(p), \ -}; \ - \ -static struct intc_vect p ## _vectors[] __initdata = { \ - INTC_IRQ_PINS_VECT_16L(p, vect), \ -}; \ - \ -static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ - INTC_IRQ_PINS_MASK_16L(p, base), \ -}; \ - \ -static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ - INTC_IRQ_PINS_PRIO_16L(p, base), \ -}; \ - \ -static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ - INTC_IRQ_PINS_SENSE_16L(p, base), \ -}; \ - \ -static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ - INTC_IRQ_PINS_ACK_16L(p, base), \ -}; \ - \ -static struct intc_desc p ## _desc __initdata = { \ - .name = str, \ - .resource = p ## _resources, \ - .num_resources = ARRAY_SIZE(p ## _resources), \ - .hw = INTC_HW_DESC(p ## _vectors, NULL, \ - p ## _mask_registers, p ## _prio_registers, \ - p ## _sense_registers, p ## _ack_registers) \ -} - -#define INTC_IRQ_PINS_16H(p, base, vect, str) \ - \ -static struct resource p ## _resources[] __initdata = { \ - [0] = { \ - .start = base, \ - .end = base + 0x64, \ - .flags = IORESOURCE_MEM, \ - }, \ -}; \ - \ -enum { \ - p ## _UNUSED = 0, \ - INTC_IRQ_PINS_ENUM_16H(p), \ -}; \ - \ -static struct intc_vect p ## _vectors[] __initdata = { \ - INTC_IRQ_PINS_VECT_16H(p, vect), \ -}; \ - \ -static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ - INTC_IRQ_PINS_MASK_16H(p, base), \ -}; \ - \ -static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ - INTC_IRQ_PINS_PRIO_16H(p, base), \ -}; \ - \ -static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ - INTC_IRQ_PINS_SENSE_16H(p, base), \ -}; \ - \ -static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ - INTC_IRQ_PINS_ACK_16H(p, base), \ -}; \ - \ -static struct intc_desc p ## _desc __initdata = { \ - .name = str, \ - .resource = p ## _resources, \ - .num_resources = ARRAY_SIZE(p ## _resources), \ - .hw = INTC_HW_DESC(p ## _vectors, NULL, \ - p ## _mask_registers, p ## _prio_registers, \ - p ## _sense_registers, p ## _ack_registers) \ -} - -#define INTC_IRQ_PINS_32(p, base, vect, str) \ - \ -static struct resource p ## _resources[] __initdata = { \ - [0] = { \ - .start = base, \ - .end = base + 0x6c, \ - .flags = IORESOURCE_MEM, \ - }, \ -}; \ - \ -enum { \ - p ## _UNUSED = 0, \ - INTC_IRQ_PINS_ENUM_16L(p), \ - INTC_IRQ_PINS_ENUM_16H(p), \ -}; \ - \ -static struct intc_vect p ## _vectors[] __initdata = { \ - INTC_IRQ_PINS_VECT_16L(p, vect), \ - INTC_IRQ_PINS_VECT_16H(p, vect), \ -}; \ - \ -static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ - INTC_IRQ_PINS_MASK_16L(p, base), \ - INTC_IRQ_PINS_MASK_16H(p, base), \ -}; \ - \ -static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ - INTC_IRQ_PINS_PRIO_16L(p, base), \ - INTC_IRQ_PINS_PRIO_16H(p, base), \ -}; \ - \ -static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ - INTC_IRQ_PINS_SENSE_16L(p, base), \ - INTC_IRQ_PINS_SENSE_16H(p, base), \ -}; \ - \ -static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ - INTC_IRQ_PINS_ACK_16L(p, base), \ - INTC_IRQ_PINS_ACK_16H(p, base), \ -}; \ - \ -static struct intc_desc p ## _desc __initdata = { \ - .name = str, \ - .resource = p ## _resources, \ - .num_resources = ARRAY_SIZE(p ## _resources), \ - .hw = INTC_HW_DESC(p ## _vectors, NULL, \ - p ## _mask_registers, p ## _prio_registers, \ - p ## _sense_registers, p ## _ack_registers) \ -} - -#define INTC_PINT_E_EMPTY -#define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0, -#define INTC_PINT_E(p) \ - PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \ - PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7, - -#define INTC_PINT_V_NONE -#define INTC_PINT_V(p, vect) \ - vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1), \ - vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3), \ - vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5), \ - vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7), - -#define INTC_PINT(p, mask_reg, sense_base, str, \ - enums_1, enums_2, enums_3, enums_4, \ - vect_1, vect_2, vect_3, vect_4, \ - mask_a, mask_b, mask_c, mask_d, \ - sense_a, sense_b, sense_c, sense_d) \ - \ -enum { \ - PINT ## p ## _UNUSED = 0, \ - enums_1 enums_2 enums_3 enums_4 \ -}; \ - \ -static struct intc_vect p ## _vectors[] __initdata = { \ - vect_1 vect_2 vect_3 vect_4 \ -}; \ - \ -static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ - { mask_reg, 0, 32, /* PINTER */ \ - { mask_a mask_b mask_c mask_d } } \ -}; \ - \ -static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ - { sense_base + 0x00, 16, 2, /* PINTCR */ \ - { sense_a } }, \ - { sense_base + 0x04, 16, 2, /* PINTCR */ \ - { sense_b } }, \ - { sense_base + 0x08, 16, 2, /* PINTCR */ \ - { sense_c } }, \ - { sense_base + 0x0c, 16, 2, /* PINTCR */ \ - { sense_d } }, \ -}; \ - \ -static struct intc_desc p ## _desc __initdata = { \ - .name = str, \ - .hw = INTC_HW_DESC(p ## _vectors, NULL, \ - p ## _mask_registers, NULL, \ - p ## _sense_registers, NULL), \ -} - -#endif /* __ASM_MACH_INTC_H */ --- 0001/arch/arm/mach-shmobile/intc-sh7372.c +++ work/arch/arm/mach-shmobile/intc-sh7372.c 2014-05-19 23:00:34.000000000 +0900 @@ -22,11 +22,10 @@ #include #include #include -#include -#include #include #include #include +#include "intc.h" enum { UNUSED_INTCA = 0, --- 0001/arch/arm/mach-shmobile/intc-sh73a0.c +++ work/arch/arm/mach-shmobile/intc-sh73a0.c 2014-05-19 23:00:40.000000000 +0900 @@ -22,14 +22,13 @@ #include #include #include -#include #include #include -#include #include #include #include #include +#include "intc.h" enum { UNUSED = 0, --- /dev/null +++ work/arch/arm/mach-shmobile/intc.h 2014-05-19 23:02:12.000000000 +0900 @@ -0,0 +1,290 @@ +#ifndef __ASM_MACH_INTC_H +#define __ASM_MACH_INTC_H +#include + +#define INTC_IRQ_PINS_ENUM_16L(p) \ + p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7, \ + p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 + +#define INTC_IRQ_PINS_ENUM_16H(p) \ + p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23, \ + p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 + +#define INTC_IRQ_PINS_VECT_16L(p, vect) \ + vect(p ## _IRQ0, 0x0200), vect(p ## _IRQ1, 0x0220), \ + vect(p ## _IRQ2, 0x0240), vect(p ## _IRQ3, 0x0260), \ + vect(p ## _IRQ4, 0x0280), vect(p ## _IRQ5, 0x02a0), \ + vect(p ## _IRQ6, 0x02c0), vect(p ## _IRQ7, 0x02e0), \ + vect(p ## _IRQ8, 0x0300), vect(p ## _IRQ9, 0x0320), \ + vect(p ## _IRQ10, 0x0340), vect(p ## _IRQ11, 0x0360), \ + vect(p ## _IRQ12, 0x0380), vect(p ## _IRQ13, 0x03a0), \ + vect(p ## _IRQ14, 0x03c0), vect(p ## _IRQ15, 0x03e0) + +#define INTC_IRQ_PINS_VECT_16H(p, vect) \ + vect(p ## _IRQ16, 0x3200), vect(p ## _IRQ17, 0x3220), \ + vect(p ## _IRQ18, 0x3240), vect(p ## _IRQ19, 0x3260), \ + vect(p ## _IRQ20, 0x3280), vect(p ## _IRQ21, 0x32a0), \ + vect(p ## _IRQ22, 0x32c0), vect(p ## _IRQ23, 0x32e0), \ + vect(p ## _IRQ24, 0x3300), vect(p ## _IRQ25, 0x3320), \ + vect(p ## _IRQ26, 0x3340), vect(p ## _IRQ27, 0x3360), \ + vect(p ## _IRQ28, 0x3380), vect(p ## _IRQ29, 0x33a0), \ + vect(p ## _IRQ30, 0x33c0), vect(p ## _IRQ31, 0x33e0) + +#define INTC_IRQ_PINS_MASK_16L(p, base) \ + { base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x44, base + 0x64, 8, /* INTMSK10A / INTMSKCLR10A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_MASK_16H(p, base) \ + { base + 0x48, base + 0x68, 8, /* INTMSK20A / INTMSKCLR20A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x4c, base + 0x6c, 8, /* INTMSK30A / INTMSKCLR30A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_PRIO_16L(p, base) \ + { base + 0x10, 0, 32, 4, /* INTPRI00A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x14, 0, 32, 4, /* INTPRI10A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_PRIO_16H(p, base) \ + { base + 0x18, 0, 32, 4, /* INTPRI20A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x1c, 0, 32, 4, /* INTPRI30A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_SENSE_16L(p, base) \ + { base + 0x00, 32, 4, /* ICR1A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x04, 32, 4, /* ICR2A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_SENSE_16H(p, base) \ + { base + 0x08, 32, 4, /* ICR3A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x0c, 32, 4, /* ICR4A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_ACK_16L(p, base) \ + { base + 0x20, 0, 8, /* INTREQ00A */ \ + { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ + p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ + { base + 0x24, 0, 8, /* INTREQ10A */ \ + { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ + p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } + +#define INTC_IRQ_PINS_ACK_16H(p, base) \ + { base + 0x28, 0, 8, /* INTREQ20A */ \ + { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ + p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ + { base + 0x2c, 0, 8, /* INTREQ30A */ \ + { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ + p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } + +#define INTC_IRQ_PINS_16(p, base, vect, str) \ + \ +static struct resource p ## _resources[] __initdata = { \ + [0] = { \ + .start = base, \ + .end = base + 0x64, \ + .flags = IORESOURCE_MEM, \ + }, \ +}; \ + \ +enum { \ + p ## _UNUSED = 0, \ + INTC_IRQ_PINS_ENUM_16L(p), \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + INTC_IRQ_PINS_VECT_16L(p, vect), \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + INTC_IRQ_PINS_MASK_16L(p, base), \ +}; \ + \ +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ + INTC_IRQ_PINS_PRIO_16L(p, base), \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + INTC_IRQ_PINS_SENSE_16L(p, base), \ +}; \ + \ +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ + INTC_IRQ_PINS_ACK_16L(p, base), \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .resource = p ## _resources, \ + .num_resources = ARRAY_SIZE(p ## _resources), \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, p ## _prio_registers, \ + p ## _sense_registers, p ## _ack_registers) \ +} + +#define INTC_IRQ_PINS_16H(p, base, vect, str) \ + \ +static struct resource p ## _resources[] __initdata = { \ + [0] = { \ + .start = base, \ + .end = base + 0x64, \ + .flags = IORESOURCE_MEM, \ + }, \ +}; \ + \ +enum { \ + p ## _UNUSED = 0, \ + INTC_IRQ_PINS_ENUM_16H(p), \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + INTC_IRQ_PINS_VECT_16H(p, vect), \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + INTC_IRQ_PINS_MASK_16H(p, base), \ +}; \ + \ +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ + INTC_IRQ_PINS_PRIO_16H(p, base), \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + INTC_IRQ_PINS_SENSE_16H(p, base), \ +}; \ + \ +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ + INTC_IRQ_PINS_ACK_16H(p, base), \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .resource = p ## _resources, \ + .num_resources = ARRAY_SIZE(p ## _resources), \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, p ## _prio_registers, \ + p ## _sense_registers, p ## _ack_registers) \ +} + +#define INTC_IRQ_PINS_32(p, base, vect, str) \ + \ +static struct resource p ## _resources[] __initdata = { \ + [0] = { \ + .start = base, \ + .end = base + 0x6c, \ + .flags = IORESOURCE_MEM, \ + }, \ +}; \ + \ +enum { \ + p ## _UNUSED = 0, \ + INTC_IRQ_PINS_ENUM_16L(p), \ + INTC_IRQ_PINS_ENUM_16H(p), \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + INTC_IRQ_PINS_VECT_16L(p, vect), \ + INTC_IRQ_PINS_VECT_16H(p, vect), \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + INTC_IRQ_PINS_MASK_16L(p, base), \ + INTC_IRQ_PINS_MASK_16H(p, base), \ +}; \ + \ +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ + INTC_IRQ_PINS_PRIO_16L(p, base), \ + INTC_IRQ_PINS_PRIO_16H(p, base), \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + INTC_IRQ_PINS_SENSE_16L(p, base), \ + INTC_IRQ_PINS_SENSE_16H(p, base), \ +}; \ + \ +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ + INTC_IRQ_PINS_ACK_16L(p, base), \ + INTC_IRQ_PINS_ACK_16H(p, base), \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .resource = p ## _resources, \ + .num_resources = ARRAY_SIZE(p ## _resources), \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, p ## _prio_registers, \ + p ## _sense_registers, p ## _ack_registers) \ +} + +#define INTC_PINT_E_EMPTY +#define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0, +#define INTC_PINT_E(p) \ + PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \ + PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7, + +#define INTC_PINT_V_NONE +#define INTC_PINT_V(p, vect) \ + vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1), \ + vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3), \ + vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5), \ + vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7), + +#define INTC_PINT(p, mask_reg, sense_base, str, \ + enums_1, enums_2, enums_3, enums_4, \ + vect_1, vect_2, vect_3, vect_4, \ + mask_a, mask_b, mask_c, mask_d, \ + sense_a, sense_b, sense_c, sense_d) \ + \ +enum { \ + PINT ## p ## _UNUSED = 0, \ + enums_1 enums_2 enums_3 enums_4 \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + vect_1 vect_2 vect_3 vect_4 \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + { mask_reg, 0, 32, /* PINTER */ \ + { mask_a mask_b mask_c mask_d } } \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + { sense_base + 0x00, 16, 2, /* PINTCR */ \ + { sense_a } }, \ + { sense_base + 0x04, 16, 2, /* PINTCR */ \ + { sense_b } }, \ + { sense_base + 0x08, 16, 2, /* PINTCR */ \ + { sense_c } }, \ + { sense_base + 0x0c, 16, 2, /* PINTCR */ \ + { sense_d } }, \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, NULL, \ + p ## _sense_registers, NULL), \ +} + +#endif /* __ASM_MACH_INTC_H */ --- 0001/arch/arm/mach-shmobile/setup-sh7372.c +++ work/arch/arm/mach-shmobile/setup-sh7372.c 2014-05-19 23:02:47.000000000 +0900 @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include --- 0001/arch/arm/mach-shmobile/setup-sh73a0.c +++ work/arch/arm/mach-shmobile/setup-sh73a0.c 2014-05-19 23:05:01.000000000 +0900 @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include