From patchwork Mon Jun 16 01:44:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 4355701 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B12FBBEEAA for ; Mon, 16 Jun 2014 01:48:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B47ED2026C for ; Mon, 16 Jun 2014 01:48:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 602AD20260 for ; Mon, 16 Jun 2014 01:48:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WwLyd-0003h3-SR; Mon, 16 Jun 2014 01:44:51 +0000 Received: from mail-bl2lp0204.outbound.protection.outlook.com ([207.46.163.204] helo=na01-bl2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WwLya-0003f4-U4 for linux-arm-kernel@lists.infradead.org; Mon, 16 Jun 2014 01:44:50 +0000 Received: from BLUPR03CA030.namprd03.prod.outlook.com (10.141.30.23) by DM2PR0301MB0639.namprd03.prod.outlook.com (25.160.96.13) with Microsoft SMTP Server (TLS) id 15.0.949.11; Mon, 16 Jun 2014 01:44:26 +0000 Received: from BN1AFFO11FD012.protection.gbl (2a01:111:f400:7c10::143) by BLUPR03CA030.outlook.office365.com (2a01:111:e400:879::23) with Microsoft SMTP Server (TLS) id 15.0.959.15 via Frontend Transport; Mon, 16 Jun 2014 01:44:25 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD012.mail.protection.outlook.com (10.58.52.72) with Microsoft SMTP Server (TLS) id 15.0.959.15 via Frontend Transport; Mon, 16 Jun 2014 01:44:25 +0000 Received: from dragon ([10.192.185.236]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s5G1iLMW031099; Sun, 15 Jun 2014 18:44:23 -0700 Date: Mon, 16 Jun 2014 09:44:16 +0800 From: Shawn Guo To: Iain Paton Subject: Re: [PATCH 2/2] ARM: dts: imx6qdl: use DT macro for clock ID Message-ID: <20140616014415.GC8860@dragon> References: <1402836147-29625-1-git-send-email-shawn.guo@freescale.com> <1402836147-29625-2-git-send-email-shawn.guo@freescale.com> <539DF957.5080603@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <539DF957.5080603@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199002)(51704005)(479174003)(24454002)(44976005)(47776003)(85852003)(83322001)(104016001)(68736004)(79102001)(33716001)(83506001)(33656002)(76482001)(80022001)(81342001)(77982001)(84676001)(21056001)(83072002)(6806004)(19580405001)(57986006)(86362001)(81542001)(575784001)(26826002)(20776003)(92726001)(1411001)(31966008)(4396001)(74502001)(76176999)(102836001)(46102001)(54356999)(50986999)(97736001)(97756001)(87936001)(46406003)(92566001)(19580395003)(74662001)(23726002)(64706001)(85306003)(99396002)(50466002)(32563001); DIR:OUT; SFP:; SCL:1; SRVR:DM2PR0301MB0639; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-Microsoft-Antispam: BL:0; ACTION:Default; RISK:Low; SCL:0; SPMLVL:NotSpam; PCL:0; RULEID: X-Forefront-PRVS: 0244637DEA Received-SPF: Fail (: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140615_184449_143773_6DF996B2 X-CRM114-Status: GOOD ( 16.04 ) X-Spam-Score: -0.7 (/) Cc: kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Sun, Jun 15, 2014 at 08:51:51PM +0100, Iain Paton wrote: > On 15/06/14 13:42, Shawn Guo wrote: > > Switch to use DT macro for clock ID, so that device tree source is more > > readable. > > [...] > > aips1: aips-bus@02000000 { > > @@ -87,7 +90,8 @@ > > compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; > > reg = <0x021f8000 0x4000>; > > interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&clks 116>; > > + /* Same clock as i.MX6Q ECSPI5 */ > > + clocks = <&clks IMX6QDL_CLK_ECSPI5>; > > status = "disabled"; > > }; > > }; > > Do you think it would it be worthwhile to define > > +#define IMX6Q_CLK_ECSPI5 116 > +#define IMX6DL_CLK_I2C4 116 > > in imx6qdl-clock.h from the first patch and use it here ? > > I'm not particularly bothered either way, I just remember thinking the > name in the enum could become a cause of confusion when I was looking > at the changes for i2c4. Yeah, point taken. Here is the change what I'm amending. Shawn --8<--------- diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 74e978841d77..b453e0e28aee 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -90,8 +90,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021f8000 0x4000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - /* Same clock as i.MX6Q ECSPI5 */ - clocks = <&clks IMX6QDL_CLK_ECSPI5>; + clocks = <&clks IMX6DL_CLK_I2C4>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 4a6cbd086da9..e9f3646d1760 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -92,8 +92,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02018000 0x4000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_ECSPI5>, - <&clks IMX6QDL_CLK_ECSPI5>; + clocks = <&clks IMX6Q_CLK_ECSPI5>, + <&clks IMX6Q_CLK_ECSPI5>; clock-names = "ipg", "per"; status = "disabled"; }; diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 84101911f1e3..e3cc1c8a1b4c 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -321,10 +321,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); if (cpu_is_imx6dl()) - /* ecspi5 is replaced with i2c4 on imx6dl & imx6s */ - clk[IMX6QDL_CLK_ECSPI5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); + clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); else - clk[IMX6QDL_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); + clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); clk[IMX6QDL_CLK_ESAI] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai); clk[IMX6QDL_CLK_ESAI_AHB] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai); diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 94700a773fe3..654151e24288 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -125,7 +125,8 @@ #define IMX6QDL_CLK_ECSPI2 113 #define IMX6QDL_CLK_ECSPI3 114 #define IMX6QDL_CLK_ECSPI4 115 -#define IMX6QDL_CLK_ECSPI5 116 +#define IMX6Q_CLK_ECSPI5 116 +#define IMX6DL_CLK_I2C4 116 #define IMX6QDL_CLK_ENET 117 #define IMX6QDL_CLK_ESAI 118 #define IMX6QDL_CLK_GPT_IPG 119