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Fri, 29 Aug 2014 01:41:30 -0700 Date: Fri, 29 Aug 2014 16:41:28 +0800 From: Shawn Guo To: Shengjiu Wang Subject: Re: [RFC PATCH 1/2] ARM: imx: add BYPASS support for PLL clocks Message-ID: <20140829084125.GB3135@dragon> References: <1409067313-32063-1-git-send-email-shawn.guo@freescale.com> <1409067313-32063-2-git-send-email-shawn.guo@freescale.com> <20140828084420.GG28777@dragon> <20140829014947.GA2741@audiosh1> <20140829025349.GH28777@dragon> <20140829033344.GA2910@audiosh1> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20140829033344.GA2910@audiosh1> User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(24454002)(199003)(51704005)(21056001)(95666004)(76482001)(81156004)(106466001)(105606002)(23726002)(107046002)(81342001)(81542001)(46406003)(46102001)(57986006)(80022001)(110136001)(83322001)(83506001)(90102001)(33656002)(19580405001)(19580395003)(33716001)(84676001)(68736004)(85306004)(69596002)(20776003)(93886004)(77982001)(64706001)(97736001)(97756001)(47776003)(79102001)(104016003)(44976005)(6806004)(26826002)(102836001)(92726001)(99396002)(50466002)(74502001)(74662001)(92566001)(83072002)(76176999)(86362001)(31966008)(85852003)(54356999)(50986999)(4396001)(87936001)(217873001); DIR:OUT; SFP:; SCL:1; SRVR:BLUPR03MB375; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 0318501FAE Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140829_014156_909784_D3969B96 X-CRM114-Status: GOOD ( 11.70 ) X-Spam-Score: -0.0 (/) Cc: Ranjani Vaidyanathan , Anson Huang , kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Fri, Aug 29, 2014 at 11:33:47AM +0800, Shengjiu Wang wrote: > Otherwise I still need to do some step in below to source the clock to ESAI. > > clk_set_parent(pll4_bypass_src, lvds2_in); > clk_set_parent(pll4_bypass, pll4_bypass_src); > clk_set_rate(pll4_audio_div, 24576000); > clk_set_rate(esai_extal, 24576000); > > I think it is what we can expect, right? if yes, the patch is ok for ESAI. Yes, we still need to set up parent and rate specifically for sabreauto ESAI use case. But these setup can be done in device tree now with commit 86be408bfbd8 (clk: Support for clock parents and rates assigned from device tree). Here is change that I tested with. (Not sure if the info in esai node is all correct) With above dts changes, I can get the following clock setup for ESAI. anaclk2 0 0 24576000 0 lvds2_in 0 0 24576000 0 pll4_bypass_src 0 0 24576000 0 pll4_bypass 0 0 24576000 0 pll4_audio 0 0 24576000 0 pll4_post_div 0 0 24576000 0 pll4_audio_div 0 0 24576000 0 esai_sel 0 0 24576000 0 esai_pred 0 0 24576000 0 esai_podf 0 0 24576000 0 esai_extal 0 0 24576000 0 Shawn diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6692115b0138..9fe4169c79dd 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -268,8 +268,18 @@ }; esai: esai@02024000 { + compatible = "fsl,imx6q-esai", "fsl,imx35-esai"; reg = <0x02024000 0x4000>; interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, + <&clks IMX6QDL_CLK_ESAI_EXTAL>, + <&clks IMX6QDL_CLK_ESAI_IPG>; + clock-names = "core", "extal", "fsys"; + dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <128>; + fsl,esai-synchronous; + status = "disabled"; }; ssi1: ssi@02028000 { diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 009abd69385d..1084394197ad 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -17,6 +17,14 @@ reg = <0x10000000 0x80000000>; }; + clocks { + anaclk2 { /* on-board 24.576MHz audio oscillator */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -45,6 +53,17 @@ }; }; +&clks { + assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, + <&clks IMX6QDL_PLL4_BYPASS>, + <&clks IMX6QDL_CLK_ESAI_SEL>, + <&clks IMX6QDL_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, + <&clks IMX6QDL_PLL4_BYPASS_SRC>, + <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <0>, <0>, <24576000>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; @@ -61,6 +80,12 @@ }; }; +&esai { + assigned-clocks = <&clks IMX6QDL_CLK_ESAI_EXTAL>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>;