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Mon, 15 Sep 2014 07:48:15 -0700 Date: Mon, 15 Sep 2014 22:48:05 +0800 From: Shawn Guo To: Shengjiu Wang Subject: Re: [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI Message-ID: <20140915144803.GL18566@dragon> References: <7ed21195ebff8b3ccbecaeb492504edd28deea2d.1410253534.git.shengjiu.wang@freescale.com> <20140915115855.GC23877@audiosh1> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20140915115855.GC23877@audiosh1> User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(199003)(189002)(24454002)(51704005)(74502001)(97756001)(74662001)(83506001)(33716001)(81542001)(86362001)(102836001)(50466002)(106466001)(77982001)(21056001)(4396001)(90102001)(92726001)(31966008)(85852003)(64706001)(23726002)(33656002)(76482001)(104016003)(46102001)(95666004)(92566001)(79102001)(57986006)(110136001)(26826002)(83072002)(46406003)(83322001)(84676001)(81342001)(105606002)(80022001)(87936001)(68736004)(20776003)(93886004)(44976005)(47776003)(107046002)(76176999)(50986999)(6806004)(85306004)(54356999)(99396002)(97736003); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR03MB329; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 03355EE97E Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140915_074909_592723_0DE7D5DF X-CRM114-Status: GOOD ( 15.62 ) X-Spam-Score: -0.2 (/) Cc: Mark Rutland , Russell King , Pawel Moll , Ian Campbell , linux-kernel , "robh+dt@kernel.org" , Sascha Hauer , Kumar Gala , Fabio Estevam , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Mon, Sep 15, 2014 at 07:58:56PM +0800, Shengjiu Wang wrote: > I add IMX6QDL_CLK_SSIx in this patch, which use share count with > IMX6QDL_CLK_SSIx_IPG. The SSI driver sound/soc/fsl/fsl_ssi.c will enable > IMX6QDL_CLK_SSIx_IPG clock in probe, but don't disable it. In the end of kernel > boot up, some one(it is not ssi driver, maybe is the clock tree) will disable > the IMX6QDL_CLK_SSIx clock, which is not enabled. IMX6QDL_CLK_SSIx_IPG share > the enable/disable bit with IMX6QDL_CLK_SSIx, So IMX6QDL_CLK_SSIx_IPG is > disabled, the aplay will fail. > > Is this the issue of imx_clk_gate2_shared()? When we want to disable IMX6QDL_CLK_SSIx, > but IMX6QDL_CLK_SSIx_IPG is enabled, can IMX6QDL_CLK_SSIx be disabled? > > > Shawn > > How do you think about this? Shengjiu, Your analysis is right. I hope the following change will get the shared gate clock code eventually does the right thing. Shawn Tested-by: Fabio Estevam diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index 84acdfd1d715..89abdf738dc9 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -97,7 +97,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw) struct clk_gate2 *gate = to_clk_gate2(hw); if (gate->share_count) - return !!(*gate->share_count); + return !!__clk_get_enable_count(hw->clk); else return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); }