From patchwork Thu May 14 16:30:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell King - ARM Linux X-Patchwork-Id: 6407471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 871D0C0432 for ; Thu, 14 May 2015 16:33:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8CB4F20251 for ; Thu, 14 May 2015 16:33:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6DF5620148 for ; Thu, 14 May 2015 16:33:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ysw2O-0005Zr-OM; Thu, 14 May 2015 16:31:08 +0000 Received: from pandora.arm.linux.org.uk ([2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ysw2F-0005O4-GM for linux-arm-kernel@lists.infradead.org; Thu, 14 May 2015 16:31:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=pandora-2014; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=Vf8B1qTQzaxd6zrnl81BrrAGhMHwCmZ0vnW5hoLjJeI=; b=LtinpLGVQLLEXQN0Vntr2boI3qmA/vJleoBL2D5RpowzbuMjKwjHXlp3TP81giAHj4tPDfkHQYEoDaOcZfUqFmQqaUaBq5Q2EP/49GdozNmiUvTowd3Zw/ijm4sojNHjmg7QynTkaZrv54BEDFIygzALtV5IOnQl/ClwwIKg+9k=; Received: from n2100.arm.linux.org.uk ([2001:4d48:ad52:3201:214:fdff:fe10:4f86]:34152) by pandora.arm.linux.org.uk with esmtpsa (TLSv1:DHE-RSA-AES256-SHA:256) (Exim 4.82_1-5b7a7c0-XX) (envelope-from ) id 1Ysw1n-0000mf-60; Thu, 14 May 2015 17:30:31 +0100 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.76) (envelope-from ) id 1Ysw1j-0007TS-QI; Thu, 14 May 2015 17:30:27 +0100 Date: Thu, 14 May 2015 17:30:27 +0100 From: Russell King - ARM Linux To: Hauke Mehrtens Subject: Re: [PATCH v2] ARM: l2c: add options to overwrite prefetching behavior Message-ID: <20150514163027.GC2067@n2100.arm.linux.org.uk> References: <1431620035-7183-1-git-send-email-hauke@hauke-m.de> <20150514161526.GB2067@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20150514161526.GB2067@n2100.arm.linux.org.uk> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150514_093059_961172_FAA85A49 X-CRM114-Status: GOOD ( 23.23 ) X-Spam-Score: -0.1 (/) Cc: devicetree@vger.kernel.org, arnd@arndb.de, geert+renesas@glider.be, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, May 14, 2015 at 05:15:26PM +0100, Russell King - ARM Linux wrote: > On Thu, May 14, 2015 at 06:13:55PM +0200, Hauke Mehrtens wrote: > > These options make it possible to overwrites the data and instruction > > prefetching behavior of the arm pl310 cache controller. > > > > We have to set these values in the aux and the prefetch register, > > because these two bits in the aux registers are mapped to the prefetch > > register. If only the prefetch register is changed there is an > > inconsistence in the state in this driver. > > No there isn't. Just set the bits in the prefetch register. > > Writing to the prefetch register changes the state of the bits in the > auxiliary control register at the same time. I see what you're getting at now. I think we ought to fix that in the driver, so that the auxiliary control register is always written first, before the prefetch control register. This also makes l2c_configure() reflect the structure of the rest of the driver. arch/arm/mm/cache-l2x0.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) Tested-by: Hauke Mehrtens diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index e309c8f35af5..46427d1a5946 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -110,14 +110,6 @@ static inline void l2c_unlock(void __iomem *base, unsigned num) static void l2c_configure(void __iomem *base) { - if (outer_cache.configure) { - outer_cache.configure(&l2x0_saved_regs); - return; - } - - if (l2x0_data->configure) - l2x0_data->configure(base); - l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); } @@ -134,7 +126,11 @@ static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock) return; l2x0_saved_regs.aux_ctrl = aux; - l2c_configure(base); + + if (outer_cache.configure) + outer_cache.configure(&l2x0_saved_regs); + else + l2x0_data->configure(base); l2c_unlock(base, num_lock); @@ -252,6 +248,7 @@ static const struct l2c_init_data l2c210_data __initconst = { .num_lock = 1, .enable = l2c_enable, .save = l2c_save, + .configure = l2c_configure, .outer_cache = { .inv_range = l2c210_inv_range, .clean_range = l2c210_clean_range, @@ -409,6 +406,7 @@ static const struct l2c_init_data l2c220_data = { .num_lock = 1, .enable = l2c220_enable, .save = l2c_save, + .configure = l2c_configure, .outer_cache = { .inv_range = l2c220_inv_range, .clean_range = l2c220_clean_range, @@ -569,6 +567,8 @@ static void l2c310_configure(void __iomem *base) { unsigned revision; + l2c_configure(base); + /* restore pl310 setup */ l2c_write_sec(l2x0_saved_regs.tag_latency, base, L310_TAG_LATENCY_CTRL); @@ -1066,6 +1066,7 @@ static const struct l2c_init_data of_l2c210_data __initconst = { .of_parse = l2x0_of_parse, .enable = l2c_enable, .save = l2c_save, + .configure = l2c_configure, .outer_cache = { .inv_range = l2c210_inv_range, .clean_range = l2c210_clean_range, @@ -1084,6 +1085,7 @@ static const struct l2c_init_data of_l2c220_data __initconst = { .of_parse = l2x0_of_parse, .enable = l2c220_enable, .save = l2c_save, + .configure = l2c_configure, .outer_cache = { .inv_range = l2c220_inv_range, .clean_range = l2c220_clean_range, @@ -1416,6 +1418,7 @@ static const struct l2c_init_data of_aurora_with_outer_data __initconst = { .enable = l2c_enable, .fixup = aurora_fixup, .save = aurora_save, + .configure = l2c_configure, .outer_cache = { .inv_range = aurora_inv_range, .clean_range = aurora_clean_range, @@ -1435,6 +1438,7 @@ static const struct l2c_init_data of_aurora_no_outer_data __initconst = { .enable = aurora_enable_no_outer, .fixup = aurora_fixup, .save = aurora_save, + .configure = l2c_configure, .outer_cache = { .resume = l2c_resume, }, @@ -1608,6 +1612,7 @@ static void __init tauros3_save(void __iomem *base) static void tauros3_configure(void __iomem *base) { + l2c_configure(base); writel_relaxed(l2x0_saved_regs.aux2_ctrl, base + TAUROS3_AUX2_CTRL); writel_relaxed(l2x0_saved_regs.prefetch_ctrl,