From patchwork Wed May 20 22:34:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 6450871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C27A2C0432 for ; Wed, 20 May 2015 22:37:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E2803202F2 for ; Wed, 20 May 2015 22:37:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 07C69202F0 for ; Wed, 20 May 2015 22:37:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YvCZa-0003I3-Ue; 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Wed, 20 May 2015 22:34:18 +0000 (UTC) Date: Wed, 20 May 2015 15:34:17 -0700 From: Stephen Boyd To: Barry Song <21cnbao@gmail.com> Subject: Re: [PATCH 1/2 v4] clk: sirf: add CSR atlas7 clk and reset support Message-ID: <20150520223417.GW31753@codeaurora.org> References: <1432111834-21178-1-git-send-email-21cnbao@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1432111834-21178-1-git-send-email-21cnbao@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150520_153440_093124_CB620462 X-CRM114-Status: GOOD ( 15.49 ) X-Spam-Score: -0.0 (/) Cc: mturquette@linaro.org, workgroup.linux@csr.com, Zhiwu Song , Barry Song , Guo Zeng , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On 05/20, Barry Song wrote: > From: Zhiwu Song > > the hardware node includes both clock and reset support, so it > is named as "car". > this patch implements Flexible clocks(mux, divider, gate), Selectable > clock(mux, divider, gate), root clock(gate),leaf clock(gate), others. > it also implements the reset controller functionality. > > Signed-off-by: Zhiwu Song > Signed-off-by: Guo Zeng > Signed-off-by: Barry Song > --- Applied to clk-next with two checkpatches squelched WARNING: __initdata should be placed after divider_list[] #740: FILE: drivers/clk/sirf/clk-atlas7.c:637: +static __initdata struct atlas7_div_init_data divider_list[] = { WARNING: static const char * array should probably be static const char * const #1061: FILE: drivers/clk/sirf/clk-atlas7.c:958: +static const char *vip_clk_parents[] = { ---8<---- diff --git a/drivers/clk/sirf/clk-atlas7.c b/drivers/clk/sirf/clk-atlas7.c index aeb6cfb4e72f..7e36d9623a4b 100644 --- a/drivers/clk/sirf/clk-atlas7.c +++ b/drivers/clk/sirf/clk-atlas7.c @@ -634,7 +634,7 @@ static struct clk_dto clk_disp1_dto = { }, }; -static __initdata struct atlas7_div_init_data divider_list[] = { +static struct atlas7_div_init_data divider_list[] __initdata = { /* div_name, parent_name, gate_name, clk_flag, divider_flag, gate_flag, div_offset, shift, wdith, gate_offset, bit_enable, lock */ { "sys0pll_qa1", "sys0pll_fixdiv", "sys0pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 0, &usbphy_div_lock }, { "sys1pll_qa1", "sys1pll_fixdiv", "sys1pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 4, &usbphy_div_lock }, @@ -955,7 +955,7 @@ static const char * const sdr_clk_parents[] = { "sys1pll_a17", }; -static const char *vip_clk_parents[] = { +static const char * const vip_clk_parents[] = { "xin", "xinw", "sys2pll_a20",