From patchwork Mon Jun 22 23:21:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 6658381 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A316CC05AC for ; Mon, 22 Jun 2015 23:23:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A9306205E5 for ; Mon, 22 Jun 2015 23:23:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A32C8205B9 for ; Mon, 22 Jun 2015 23:23:23 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z7B25-0007VC-2P; Mon, 22 Jun 2015 23:21:41 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z7B21-0007QD-7h for linux-arm-kernel@lists.infradead.org; Mon, 22 Jun 2015 23:21:37 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 2859C1411EB; Mon, 22 Jun 2015 23:21:16 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 008FA1411EE; Mon, 22 Jun 2015 23:21:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: sboyd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E1E341411EB; Mon, 22 Jun 2015 23:21:14 +0000 (UTC) Date: Mon, 22 Jun 2015 16:21:14 -0700 From: Stephen Boyd To: Daniel Thompson Subject: Re: [PATCH v3 2/3] clk: stm32: Add clock driver for STM32F4[23]xxx devices Message-ID: <20150622232114.GK22132@codeaurora.org> References: <1432327273-6810-1-git-send-email-daniel.thompson@linaro.org> <1433966978-24422-1-git-send-email-daniel.thompson@linaro.org> <1433966978-24422-3-git-send-email-daniel.thompson@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1433966978-24422-3-git-send-email-daniel.thompson@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150622_162137_313716_F2646837 X-CRM114-Status: GOOD ( 20.94 ) X-Spam-Score: -3.3 (---) Cc: Mark Rutland , devicetree@vger.kernel.org, linaro-kernel@lists.linaro.org, Mike Turquette , Pawel Moll , Ian Campbell , patches@linaro.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Kamil Lulko , Rob Herring , Maxime Coquelin , Kumar Gala , Russell King , Andreas Farber , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On 06/10, Daniel Thompson wrote: > The driver supports decoding and statically modelling PLL state (i.e. > we inherit state from bootloader) and provides support for all > peripherals that support simple one-bit gated clocks. The covers all > peripherals whose clocks come from the AHB, APB1 or APB2 buses. > > It has been tested on an STM32F429I-Discovery board. The clock counts > for TIM2, USART1 and SYSTICK are all set correctly and the wall clock > looks OK when checked with a stopwatch. I have also tested a prototype > driver for the RNG hardware. The RNG clock is correctly enabled by the > framework (also did inverse test and proved that by changing DT to > configure the wrong clock bit then we observe the RNG driver to fail). > > Signed-off-by: Daniel Thompson > Reviewed-by: Maxime Coquelin I also squashed in some sparse fixes. Please check. drivers/clk/clk-stm32f4.c:135:44: warning: constant 0x000000f17ef417ff is so big it is long drivers/clk/clk-stm32f4.c:137:44: warning: constant 0x04777f33f6fec9ff is so big it is long drivers/clk/clk-stm32f4.c:206:12: warning: symbol 'clk_register_apb_mul' was not declared. Should it be static? drivers/clk/clk-stm32f4.c:285:12: warning: symbol 'stm32f4_rcc_lookup_clk' was not declared. Should it be static? ---8<---- diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index c825bbd4335f..b9b12a742970 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -132,9 +132,9 @@ enum { SYSTICK, FCLK }; * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx * have gate bits associated with them. Its combined hweight is 71. */ -static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ff, - 0x0000000000000001, - 0x04777f33f6fec9ff }; +static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ffull, + 0x0000000000000001ull, + 0x04777f33f6fec9ffull }; static struct clk *clks[MAX_CLKS]; static DEFINE_SPINLOCK(stm32f4_clk_lock); @@ -186,7 +186,7 @@ static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate, } static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) + unsigned long parent_rate) { /* * We must report success but we can do so unconditionally because @@ -203,9 +203,9 @@ static const struct clk_ops clk_apb_mul_factor_ops = { .recalc_rate = clk_apb_mul_recalc_rate, }; -struct clk *clk_register_apb_mul(struct device *dev, const char *name, - const char *parent_name, unsigned long flags, - u8 bit_idx) +static struct clk *clk_register_apb_mul(struct device *dev, const char *name, + const char *parent_name, + unsigned long flags, u8 bit_idx) { struct clk_apb_mul *am; struct clk_init_data init; @@ -282,7 +282,8 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary) (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0); } -struct clk *stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) +static struct clk * +stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) { int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);