@@ -587,7 +587,7 @@ static void dfll_load_i2c_lut(struct tegra_dfll *td)
else
lut_index = i;
- val = regulator_list_hardware_vsel(td->vdd_reg,
+ val = regulator_list_hardware_vsel(td->vdd_reg,
td->i2c_lut[lut_index]);
__raw_writel(val, td->lut_base + i * 4);
}
@@ -1432,6 +1432,7 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td)
int selector;
unsigned long rate;
struct dev_pm_opp *opp;
+ int lut;
rcu_read_lock();
@@ -1444,9 +1445,10 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td)
v_max = dev_pm_opp_get_voltage(opp);
v = td->soc->min_millivolts * 1000;
- td->i2c_lut[0] = find_vdd_map_entry_exact(td, v);
- if (td->i2c_lut[0] < 0)
+ lut = find_vdd_map_entry_exact(td, v);
+ if (lut < 0)
goto out;
+ td->i2c_lut[0] = lut;
for (j = 1, rate = 0; ; rate++) {
opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
@@ -1447,7 +1447,7 @@ static void tegra124_car_barrier(void)
*
* Assert the reset line of the DFLL's DVCO. No return value.
*/
-void tegra124_clock_assert_dfll_dvco_reset(void)
+static void tegra124_clock_assert_dfll_dvco_reset(void)
{
u32 v;
@@ -1463,7 +1463,7 @@ void tegra124_clock_assert_dfll_dvco_reset(void)
* Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
* operate. No return value.
*/
-void tegra124_clock_deassert_dfll_dvco_reset(void)
+static void tegra124_clock_deassert_dfll_dvco_reset(void)
{
u32 v;
@@ -1473,7 +1473,7 @@ void tegra124_clock_deassert_dfll_dvco_reset(void)
tegra124_car_barrier();
}
-int tegra124_reset_assert(unsigned long id)
+static int tegra124_reset_assert(unsigned long id)
{
if (id == TEGRA124_RST_DFLL_DVCO)
tegra124_clock_assert_dfll_dvco_reset();
@@ -1483,7 +1483,7 @@ int tegra124_reset_assert(unsigned long id)
return 0;
}
-int tegra124_reset_deassert(unsigned long id)
+static int tegra124_reset_deassert(unsigned long id)
{
if (id == TEGRA124_RST_DFLL_DVCO)
tegra124_clock_deassert_dfll_dvco_reset();