From patchwork Sun Dec 6 09:04:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Francois Moine X-Patchwork-Id: 7778371 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6B45EBEEE1 for ; Sun, 6 Dec 2015 09:09:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D48C4203DA for ; Sun, 6 Dec 2015 09:09:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DBC48203C4 for ; Sun, 6 Dec 2015 09:09:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a5VGR-0002HI-OH; Sun, 06 Dec 2015 09:05:52 +0000 Received: from smtp5-g21.free.fr ([2a01:e0c:1:1599::14]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a5VFK-0007iZ-Hw for linux-arm-kernel@lists.infradead.org; Sun, 06 Dec 2015 09:05:20 +0000 Received: from void-opi2 (unknown [82.245.201.222]) by smtp5-g21.free.fr (Postfix) with SMTP id C2C1FD48065; Sun, 6 Dec 2015 10:03:16 +0100 (CET) Date: Sun, 6 Dec 2015 10:04:12 +0100 From: Jean-Francois Moine To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Michael Turquette , Stephen Boyd , Linus Walleij Subject: [PATCH] clk: sunxi: Extend the simple gates and handle the Allwinner H3 Message-Id: <20151206100412.1a74b71da8e9ca28c6e61589@free.fr> X-Mailer: Sylpheed 3.4.3 (GTK+ 2.24.28; armv7l-unknown-linux-gnueabihf) Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151206_010445_613196_060290CF X-CRM114-Status: GOOD ( 13.02 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Vishnu Patekar , Emilio =?ISO-8859-1?Q?L=F3pez?= , Reinder de Haan , linux-kernel@vger.kernel.org, Hans de Goede , linux-sunxi@googlegroups.com, Jens Kuske , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The H3 has a clock gate definition similar to the other Allwinner SoCs, but with a different parent clock for each single gate. Adding the names of the parent clocks in both the source and output clocks permits the use of the simple-gates driver to define the bus gates of all known Allwinner SoCs. Signed-off-by: Jean-Francois Moine --- This patch replaces a part of Jens Kuske's patch [PATCH v5 1/4] clk: sunxi: Add H3 clocks support --- Documentation/devicetree/bindings/clock/sunxi.txt | 25 +++++++++++++++++++++++ drivers/clk/sunxi/clk-simple-gates.c | 14 ++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 8a47b77..5736e6d 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -70,6 +70,7 @@ Required properties: "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 + "allwinner,sunxi-gates-clk" - simple gates Required properties for all clocks: - reg : shall be the control register address for the clock. @@ -93,6 +94,12 @@ The "allwinner,sun9i-a80-mmc-config-clk" clock also requires: - #reset-cells : shall be set to 1 - resets : shall be the reset control phandle for the mmc block. +The "allwinner,sunxi-gates-clk" clock also requires: +- clock-names : corresponding names of the parent clocks +when the output clocks have different parents. +These names must be 4 characters long and must appear as a prefix in +the names of the output clocks. See example. + For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate dummy clocks at 25 MHz and 125 MHz, respectively. See example. @@ -203,3 +210,21 @@ mmc_config_clk: clk@01c13000 { clock-output-names = "mmc0_config", "mmc1_config", "mmc2_config", "mmc3_config"; }; + +bus_gates: clk@01c20060 { + compatible = "allwinner,sunxi-gates-clk"; + reg = <0x01c20060 0x14>; + clocks = <&ahb1>, <&ahb2>; + clock-names = "ahb1", "ahb2"; + clock-indices = <5>, <6>, <8>, + <17>, <18>, + <26>, <27>, + <28>, <29>, + <128>, <135>; + clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", + "ahb2_emac", "ahb1_ts", + "ahb1_ehci2", "ahb1_ehci3", + "ahb1_otg_ohci0", "ahb2_ohci1", + "ahb1_ephy", "ahb1_dbg"; + }; +}; diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c index 0214c65..81c4cb0 100644 --- a/drivers/clk/sunxi/clk-simple-gates.c +++ b/drivers/clk/sunxi/clk-simple-gates.c @@ -29,12 +29,14 @@ static void __init sunxi_simple_gates_setup(struct device_node *node, { struct clk_onecell_data *clk_data; const char *clk_parent, *clk_name; + char dyn_clk_parent[8]; struct property *prop; struct resource res; void __iomem *clk_reg; void __iomem *reg; const __be32 *p; int number, i = 0, j; + bool parent_per_gate; u8 clk_bit; u32 index; @@ -42,7 +44,13 @@ static void __init sunxi_simple_gates_setup(struct device_node *node, if (IS_ERR(reg)) return; - clk_parent = of_clk_get_parent_name(node, 0); + parent_per_gate = of_clk_get_parent_count(node) != 1; + if (parent_per_gate) { + clk_parent = dyn_clk_parent; + dyn_clk_parent[4] = '\0'; + } else { + clk_parent = of_clk_get_parent_name(node, 0); + } clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); if (!clk_data) @@ -58,6 +66,8 @@ static void __init sunxi_simple_gates_setup(struct device_node *node, of_property_for_each_u32(node, "clock-indices", prop, p, index) { of_property_read_string_index(node, "clock-output-names", i, &clk_name); + if (parent_per_gate) + strncpy(dyn_clk_parent, clk_name, 4); clk_reg = reg + 4 * (index / 32); clk_bit = index % 32; @@ -140,6 +150,8 @@ CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk", sunxi_simple_gates_init); CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk", sunxi_simple_gates_init); +CLK_OF_DECLARE(sunxi_gates, "allwinner,sunxi-gates-clk",sunxi-gates + sunxi_simple_gates_init); static const int sun4i_a10_ahb_critical_clocks[] __initconst = { 14, /* ahb_sdram */