From patchwork Mon Jun 27 09:02:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 9200071 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 91C2060752 for ; Mon, 27 Jun 2016 09:04:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 810341FF29 for ; Mon, 27 Jun 2016 09:04:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 756FE27FBC; Mon, 27 Jun 2016 09:04:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1861B1FF29 for ; Mon, 27 Jun 2016 09:04:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bHSRR-0008Rv-Uf; Mon, 27 Jun 2016 09:02:53 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bHSRE-0008Kz-Qm for linux-arm-kernel@lists.infradead.org; Mon, 27 Jun 2016 09:02:41 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 27 Jun 2016 02:02:20 -0700 Received: from HQHUB102.nvidia.com ([172.20.187.25]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 27 Jun 2016 02:01:15 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 27 Jun 2016 02:01:15 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQHUB102.nvidia.com (172.20.187.25) with Microsoft SMTP Server (TLS) id 8.3.406.0; Mon, 27 Jun 2016 02:02:23 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Mon, 27 Jun 2016 09:02:23 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Mon, 27 Jun 2016 09:02:23 +0000 Received: from jlo-ubuntu64.nvidia.com (Not Verified[10.19.108.111]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,5,8150) id ; Mon, 27 Jun 2016 02:02:23 -0700 From: Joseph Lo To: Stephen Warren , Thierry Reding , Alexandre Courbot Subject: [PATCH 01/10] Documentation: dt-bindings: mailbox: tegra: Add binding for HSP mailbox Date: Mon, 27 Jun 2016 17:02:39 +0800 Message-ID: <20160627090248.23621-2-josephl@nvidia.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160627090248.23621-1-josephl@nvidia.com> References: <20160627090248.23621-1-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160627_020240_929425_71D87C28 X-CRM114-Status: GOOD ( 15.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Catalin Marinas , Peter De Schrijver , Jassi Brar , Will Deacon , linux-kernel@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org, Joseph Lo , linux-tegra@vger.kernel.org, Matthew Longnecker Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT binding for the Hardware Synchronization Primitives (HSP). The HSP is designed for the processors to share resources and communicate together. It provides a set of hardware synchronization primitives for interprocessor communication. So the interprocessor communication (IPC) protocols can use hardware synchronization primitive, when operating between two processors not in an SMP relationship. Signed-off-by: Joseph Lo --- .../bindings/mailbox/nvidia,tegra186-hsp.txt | 42 ++++++++++++++++++++++ include/dt-bindings/mailbox/tegra-hsp.h | 20 +++++++++++ 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt create mode 100644 include/dt-bindings/mailbox/tegra-hsp.h diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt new file mode 100644 index 000000000000..ca07af2d951e --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt @@ -0,0 +1,42 @@ +NVIDIA Tegra Hardware Synchronization Primitives (HSP) + +The HSP modules are used for the processors to share resources and communicate +together. It provides a set of hardware synchronization primitives for +interprocessor communication. So the interprocessor communication (IPC) +protocols can use hardware synchronization primitives, when operating between +two processors not in an SMP relationship. + +The features that HSP supported are shared mailboxes, shared semaphores, +arbitrated semaphores and doorbells. + +Required properties: +- name : Should be hsp +- compatible : Should be "nvidia,tegra-hsp" +- reg : Offset and length of the register set for the device +- interrupts : Should contain the HSP interrupts +- interrupt-names: Should contain the names of the HSP interrupts that the + client are using. + "doorbell" +- nvidia,hsp-function : Specifies one of the HSP functions that the HSP unit + will be supported. The function ID can be found in the + header file . +- #mbox-cells : Should be 1. Specifies the HSP master that will be enabled of + the HSP client. The master ID constants can be found in the + header file . + +Example: + +hsp_top: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x0 0x03c00000 0x0 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + nvidia,hsp-function = ; + #mbox-cells = <1>; +}; + +bpmp@d0000000 { + ... + mboxes = <&hsp_top HSP_DB_MASTER_BPMP>; + ... +}; diff --git a/include/dt-bindings/mailbox/tegra-hsp.h b/include/dt-bindings/mailbox/tegra-hsp.h new file mode 100644 index 000000000000..720c66784b72 --- /dev/null +++ b/include/dt-bindings/mailbox/tegra-hsp.h @@ -0,0 +1,20 @@ +/* + * This header provides constants for binding nvidia,tegra-hsp. + * + * The number with HSP_DB_MASTER prefix indicates the bit that is + * associated with a master ID in the doorbell registers. + */ + + +#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H +#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H + +#define HSP_SHARED_MAILBOX 0 +#define HSP_SHARED_SEMAPHORE 1 +#define HSP_ARBITRATED_SEMAPHORE 2 +#define HSP_DOORBELL 3 + +#define HSP_DB_MASTER_CCPLEX 17 +#define HSP_DB_MASTER_BPMP 19 + +#endif /* _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H */