From patchwork Mon Jun 27 09:02:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 9200075 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0E93860752 for ; Mon, 27 Jun 2016 09:04:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EFE5A1FF29 for ; Mon, 27 Jun 2016 09:04:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E44D427FBC; Mon, 27 Jun 2016 09:04:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 612011FF29 for ; Mon, 27 Jun 2016 09:04:55 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bHSRy-0000Ls-LM; Mon, 27 Jun 2016 09:03:26 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bHSRR-0008Ly-Pn for linux-arm-kernel@lists.infradead.org; Mon, 27 Jun 2016 09:02:54 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 27 Jun 2016 02:02:00 -0700 Received: from HQMAIL101.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 27 Jun 2016 02:01:24 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 27 Jun 2016 02:01:24 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Mon, 27 Jun 2016 09:02:31 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Mon, 27 Jun 2016 09:02:32 +0000 Received: from jlo-ubuntu64.nvidia.com (Not Verified[10.19.108.111]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Mon, 27 Jun 2016 02:02:31 -0700 From: Joseph Lo To: Stephen Warren , Thierry Reding , Alexandre Courbot Subject: [PATCH 03/10] Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP Date: Mon, 27 Jun 2016 17:02:41 +0800 Message-ID: <20160627090248.23621-4-josephl@nvidia.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160627090248.23621-1-josephl@nvidia.com> References: <20160627090248.23621-1-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160627_020253_954029_6385A57D X-CRM114-Status: GOOD ( 13.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Catalin Marinas , Peter De Schrijver , Jassi Brar , Will Deacon , linux-kernel@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org, Joseph Lo , linux-tegra@vger.kernel.org, Matthew Longnecker Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The BPMP is a specific processor in Tegra chip, which is designed for booting process handling and offloading the power management tasks from the CPU. The binding document defines the resources that would be used by the BPMP firmware driver, which can create the interprocessor communication (IPC) between the CPU and BPMP. Signed-off-by: Joseph Lo --- .../bindings/firmware/nvidia,tegra186-bpmp.txt | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt new file mode 100644 index 000000000000..34a252d87e17 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt @@ -0,0 +1,61 @@ +NVIDIA Tegra Boot and Power Management Processor (BPMP) + +The BPMP is a specific processor in Tegra chip, which is designed for +booting process handling and offloading the power management tasks from +the CPU. The binding document defines the resources that would be used by +the BPMP firmware driver, which can create the interprocessor +communication (IPC) between the CPU and BPMP. + +Required properties: +- name : Should be bpmp +- compatible : Should be "nvidia,tegra-bpmp" +- mboxes : The phandle of mailbox controller and the channel ID + See "Documentation/devicetree/bindings/mailbox/ + nvidia,tegra186-hsp.txt" and "Documentation/devicetree/ + bindings/mailbox/mailbox.txt" for more details about the generic + mailbox controller and mailbox client driver bindings. +- shmem : List of the phandle of the TX and RX shared memory area that + the IPC between CPU and BPMP is based on. +- #clock-cells : Should be 1. +- #reset-cells : Should be 1. + +The shared memory bindings for BPMP +----------------------------------- + +The shared memory area for the IPC TX and RX between CPU and BPMP are +predefined and work on top of sysram, which is a sram inside the chip. + +See "Documentation/devicetree/bindings/sram/sram.txt" for the bindings. + +Example: + +hsp_top: hsp@03c00000 { + ... + #mbox-cells = <1>; +}; + +bpmp@d0000000 { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp_mbox HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + #clock-cells = <1>; + #reset-cells = <1>; +}; + +sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-ram"; + reg = <0x0 0x30000000 0x0 0x50000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + + cpu_bpmp_tx: bpmp_shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + }; + + cpu_bpmp_rx: bpmp_shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + }; +};