diff mbox

arm64: tegra: Enable all cores on Jetson TX1

Message ID 20160630080119.27090-1-acourbot@nvidia.com (mailing list archive)
State New, archived
Headers show

Commit Message

Alexandre Courbot June 30, 2016, 8:01 a.m. UTC
Enable PSCI firmware and all 4 cores of T210 on Jetson TX1.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
Not sure why this was not done - in any case this seems to work fine
and performance is obviously improved (especially boot time).

 arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Thierry Reding June 30, 2016, 9:22 a.m. UTC | #1
On Thu, Jun 30, 2016 at 05:01:19PM +0900, Alexandre Courbot wrote:
> Enable PSCI firmware and all 4 cores of T210 on Jetson TX1.
> 
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---
> Not sure why this was not done - in any case this seems to work fine
> and performance is obviously improved (especially boot time).
> 
>  arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)

The reason why this wasn't done initially is because the firmware was
supposed to copy this data into the device tree before passing it to the
kernel. The rationale for this decision was that we can't make any
assumptions about the firmware and any potential PSCI implementation.

I suppose the firmware interface could be argued to be part of the
hardware and therefore having it statically in DT would be okay. The one
remaining issue is that it is possible to boot a Tegra X1 without any
secure firmware that might provide PSCI, in which case the DT would now
be lying.

Thierry
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index bb319daf6aa5..6e7fe0517e5c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -71,4 +71,27 @@ 
 			regulator-enable-ramp-delay = <1000>;
 		};
 	};
+
+	cpus {
+		cpu@0 {
+			enable-method = "psci";
+		};
+
+		cpu@1 {
+			enable-method = "psci";
+		};
+
+		cpu@2 {
+			enable-method = "psci";
+		};
+
+		cpu@3 {
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
 };