From patchwork Tue Jul 5 09:04:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 9213887 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7547C6048B for ; Tue, 5 Jul 2016 09:08:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 638912893D for ; Tue, 5 Jul 2016 09:08:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5809E28975; Tue, 5 Jul 2016 09:08:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 087EB2893D for ; Tue, 5 Jul 2016 09:08:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bKMJk-0005JI-69; Tue, 05 Jul 2016 09:06:56 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bKMIb-0003vs-V6 for linux-arm-kernel@lists.infradead.org; Tue, 05 Jul 2016 09:05:48 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 05 Jul 2016 02:04:43 -0700 Received: from HQMAIL103.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 05 Jul 2016 02:03:52 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 05 Jul 2016 02:03:52 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 5 Jul 2016 09:05:25 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 5 Jul 2016 09:05:25 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 5 Jul 2016 09:05:25 +0000 Received: from jlo-ubuntu64.nvidia.com (Not Verified[10.19.108.111]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 05 Jul 2016 02:05:24 -0700 From: Joseph Lo To: Stephen Warren , Thierry Reding , Alexandre Courbot Subject: [PATCH V2 08/10] arm64: dts: tegra: Add Tegra186 support Date: Tue, 5 Jul 2016 17:04:29 +0800 Message-ID: <20160705090431.5852-9-josephl@nvidia.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160705090431.5852-1-josephl@nvidia.com> References: <20160705090431.5852-1-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160705_020546_262983_A038925A X-CRM114-Status: GOOD ( 12.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Catalin Marinas , Peter De Schrijver , Jassi Brar , Will Deacon , linux-kernel@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org, Joseph Lo , linux-tegra@vger.kernel.org, Matthew Longnecker Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the initial support of Tegra186 SoC, which can help to bring up the debug console and initrd for further developing. Signed-off-by: Joseph Lo --- Changes in V2: - update the file according the HSP and BPMP binding fix in V2 --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 77 ++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra186.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi new file mode 100644 index 000000000000..57badd5de9b4 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -0,0 +1,77 @@ +#include +#include + +/ { + compatible = "nvidia,tegra186"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + uarta: serial@03100000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x03100000 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + status = "disabled"; + }; + + gic: interrupt-controller@03881000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x03881000 0x0 0x1000>, + <0x0 0x03882000 0x0 0x2000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + hsp_top0: hsp@03c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x0 0x03c00000 0x0 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <1>; + status = "disabled"; + }; + + sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-ram"; + reg = <0x0 0x30000000 0x0 0x4ffff>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x4ffff>; + + cpu_bpmp_tx: bpmp_shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + }; + + cpu_bpmp_rx: bpmp_shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + }; + }; + + bpmp { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp_top0 HSP_MBOX_ID(DB, HSP_DB_MASTER_BPMP)>; + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + #clock-cells = <1>; + #reset-cells = <1>; + status = "disabled"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; +};