From patchwork Tue Jul 19 09:17:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 9236561 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3E1886075D for ; Tue, 19 Jul 2016 09:20:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C9CF20072 for ; Tue, 19 Jul 2016 09:20:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2115A2624D; Tue, 19 Jul 2016 09:20:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8268320072 for ; Tue, 19 Jul 2016 09:20:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bPRAm-0002wX-BJ; Tue, 19 Jul 2016 09:18:40 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bPRAT-0002lu-Sm for linux-arm-kernel@lists.infradead.org; Tue, 19 Jul 2016 09:18:27 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 19 Jul 2016 02:17:59 -0700 Received: from HQMAIL103.nvidia.com ([172.20.187.11]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 19 Jul 2016 02:15:42 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 19 Jul 2016 02:15:42 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 19 Jul 2016 09:17:59 +0000 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 19 Jul 2016 09:17:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 19 Jul 2016 09:17:59 +0000 Received: from jlo-ubuntu64.nvidia.com (Not Verified[10.19.108.111]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 19 Jul 2016 02:17:59 -0700 From: Joseph Lo To: Stephen Warren , Thierry Reding , Alexandre Courbot Subject: [PATCH V3 01/10] Documentation: dt-bindings: mailbox: tegra: Add binding for HSP mailbox Date: Tue, 19 Jul 2016 17:17:22 +0800 Message-ID: <20160719091723.30919-1-josephl@nvidia.com> X-Mailer: git-send-email 2.9.2 X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160719_021822_055776_2FCF1F5B X-CRM114-Status: GOOD ( 15.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Catalin Marinas , Peter De Schrijver , Jassi Brar , Will Deacon , linux-kernel@vger.kernel.org, Sivaram Nair , Rob Herring , linux-arm-kernel@lists.infradead.org, Joseph Lo , linux-tegra@vger.kernel.org, Matthew Longnecker Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT binding for the Hardware Synchronization Primitives (HSP). The HSP is designed for the processors to share resources and communicate together. It provides a set of hardware synchronization primitives for interprocessor communication. So the interprocessor communication (IPC) protocols can use hardware synchronization primitive, when operating between two processors not in an SMP relationship. Signed-off-by: Joseph Lo Acked-by: Stephen Warren Acked-by: Rob Herring Acked-by: Jon Hunter --- Sorry. Please allow me just update the binding patches of this series. Want to make sure the binding is acceptable first. Thanks. Changes in V3: - use two cells for mboxes property Changes in V2: - revise the compatible string, interrupt-names, interrupts, and #mbox-cells properties - remove "nvidia,hsp-function" property - fix the header file name - the binding supports the concept of multiple HSP sub-modules on one HSP HW block now. --- .../bindings/mailbox/nvidia,tegra186-hsp.txt | 52 ++++++++++++++++++++++ include/dt-bindings/mailbox/tegra186-hsp.h | 20 +++++++++ 2 files changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt create mode 100644 include/dt-bindings/mailbox/tegra186-hsp.h diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt new file mode 100644 index 000000000000..a9152380642d --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt @@ -0,0 +1,52 @@ +NVIDIA Tegra Hardware Synchronization Primitives (HSP) + +The HSP modules are used for the processors to share resources and communicate +together. It provides a set of hardware synchronization primitives for +interprocessor communication. So the interprocessor communication (IPC) +protocols can use hardware synchronization primitives, when operating between +two processors not in an SMP relationship. + +The features that HSP supported are shared mailboxes, shared semaphores, +arbitrated semaphores and doorbells. + +Required properties: +- name : Should be hsp +- compatible + Array of strings. + one of: + - "nvidia,tegra186-hsp" +- reg : Offset and length of the register set for the device. +- interrupt-names + Array of strings. + Contains a list of names for the interrupts described by the interrupt + property. May contain the following entries, in any order: + - "doorbell" + Users of this binding MUST look up entries in the interrupt property + by name, using this interrupt-names property to do so. +- interrupts + Array of interrupt specifiers. + Must contain one entry per entry in the interrupt-names property, + in a matching order. +- #mbox-cells : Should be 2. + +The mbox specifier of the "mboxes" property in the client node should +contain two data. The first one should be the HSP type and the second +one should be the ID that the client is going to use. Those information +can be found in the following file. + +- . + +Example: + +hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x0 0x03c00000 0x0 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; +}; + +client { + ... + mboxes = <&hsp_top0 HSP_MBOX_TYPE_DB HSP_DB_MASTER_XXX>; +}; diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h new file mode 100644 index 000000000000..d1c1432707cd --- /dev/null +++ b/include/dt-bindings/mailbox/tegra186-hsp.h @@ -0,0 +1,20 @@ +/* + * This header provides constants for binding nvidia,tegra186-hsp. + * + * The number with HSP_DB_MASTER prefix indicates the bit that is + * associated with a master ID in the doorbell registers. + */ + + +#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H +#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H + +#define HSP_MBOX_TYPE_DB 0x0 +#define HSP_MBOX_TYPE_SM 0x1 +#define HSP_MBOX_TYPE_SS 0x2 +#define HSP_MBOX_TYPE_AS 0x3 + +#define HSP_DB_MASTER_CCPLEX 17 +#define HSP_DB_MASTER_BPMP 19 + +#endif /* _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H */