[v4,4/5] net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC

Message ID	20160904182320.671-5-martin.blumenstingl@googlemail.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> To: linux-amlogic@lists.infradead.org, khilman@baylibre.com, carlo@caione.org, mturquette@baylibre.com, peppe.cavallaro@st.com, alexandre.torgue@st.com Subject: [PATCH v4 4/5] net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC Date: Sun, 4 Sep 2016 20:23:19 +0200 Message-Id: <20160904182320.671-5-martin.blumenstingl@googlemail.com> In-Reply-To: <20160904182320.671-1-martin.blumenstingl@googlemail.com> References: <20160828161637.9941-1-martin.blumenstingl@googlemail.com> <20160904182320.671-1-martin.blumenstingl@googlemail.com> Precedence: list Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, arnd@arndb.de, Martin Blumenstingl <martin.blumenstingl@googlemail.com>, catalin.marinas@arm.com, manabian@gmail.com, will.deacon@arm.com, davem@davemloft.net, robh+dt@kernel.org, netdev@vger.kernel.org, sboyd@codeaurora.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org

Hi Martin, [auto build test ERROR on next-20160825] [also build test ERROR on v4.8-rc5] [cannot apply to robh/for-next net-next/master net/master v4.8-rc4 v4.8-rc3 v4.8-rc2] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] [Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on] [Check https://git-scm.com/docs/git-format-patch for more information] url: https://github.com/0day-ci/linux/commits/Martin-Blumenstingl/meson-Meson8b-and-GXBB-DWMAC-glue-driver/20160905-023130 config: sparc64-allyesconfig (attached as .config) compiler: sparc64-linux-gnu-gcc (Debian 5.4.0-6) 5.4.0 20160609 reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=sparc64 All error/warnings (new ones prefixed by >>): >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:63:18: error: field 'm250_mux' has incomplete type struct clk_mux m250_mux; ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:67:21: error: field 'm250_div' has incomplete type struct clk_divider m250_div; ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:70:21: error: field 'm25_div' has incomplete type struct clk_divider m25_div; ^ drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c: In function 'meson8b_init_clk': >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:88:23: error: storage size of 'init' isn't known struct clk_init_data init; ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:94:30: error: array type has incomplete element type 'struct clk_div_table' static struct clk_div_table clk_25m_div_table[] = { ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:95:5: error: field name not in record or union initializer { .val = 0, .div = 5 }, ^ drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:95:5: note: (near initialization for 'clk_25m_div_table') drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:95:15: error: field name not in record or union initializer { .val = 0, .div = 5 }, ^ drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:95:15: note: (near initialization for 'clk_25m_div_table') drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:96:5: error: field name not in record or union initializer { .val = 1, .div = 10 }, ^ drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:96:5: note: (near initialization for 'clk_25m_div_table') drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:96:15: error: field name not in record or union initializer { .val = 1, .div = 10 }, ^ drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:96:15: note: (near initialization for 'clk_25m_div_table') >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:114:4: error: implicit declaration of function '__clk_get_name' [-Werror=implicit-function-declaration] __clk_get_name(dwmac->m250_mux_parent[i]); ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:113:23: warning: assignment makes pointer from integer without a cast [-Wint-conversion] mux_parent_names[i] = ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:120:14: error: 'clk_mux_ops' undeclared (first use in this function) init.ops = &clk_mux_ops; ^ drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:120:14: note: each undeclared identifier is reported only once for each function it appears in >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:132:24: error: implicit declaration of function 'devm_clk_register' [-Werror=implicit-function-declaration] dwmac->m250_mux_clk = devm_clk_register(dev, &dwmac->m250_mux.hw); ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:139:14: error: 'clk_divider_ops' undeclared (first use in this function) init.ops = &clk_divider_ops; ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:140:15: error: 'CLK_SET_RATE_PARENT' undeclared (first use in this function) init.flags = CLK_SET_RATE_PARENT; ^ drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:141:21: warning: assignment makes pointer from integer without a cast [-Wint-conversion] clk_div_parents[0] = __clk_get_name(dwmac->m250_mux_clk); ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:149:26: error: 'CLK_DIVIDER_ONE_BASED' undeclared (first use in this function) dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:149:50: error: 'CLK_DIVIDER_ALLOW_ZERO' undeclared (first use in this function) dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:159:15: error: 'CLK_IS_BASIC' undeclared (first use in this function) init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; ^ drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:160:21: warning: assignment makes pointer from integer without a cast [-Wint-conversion] clk_div_parents[0] = __clk_get_name(dwmac->m250_div_clk); ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:94:30: warning: unused variable 'clk_25m_div_table' [-Wunused-variable] static struct clk_div_table clk_25m_div_table[] = { ^ >> drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c:88:23: warning: unused variable 'init' [-Wunused-variable] struct clk_init_data init; ^ cc1: some warnings being treated as errors vim +/m250_mux +63 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c 57 struct platform_device *pdev; 58 59 void __iomem *regs; 60 61 phy_interface_t phy_mode; 62 > 63 struct clk_mux m250_mux; 64 struct clk *m250_mux_clk; 65 struct clk *m250_mux_parent[MUX_CLK_NUM_PARENTS]; 66 > 67 struct clk_divider m250_div; 68 struct clk *m250_div_clk; 69 > 70 struct clk_divider m25_div; 71 struct clk *m25_div_clk; 72 }; 73 74 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, 75 u32 mask, u32 value) 76 { 77 u32 data; 78 79 data = readl(dwmac->regs + reg); 80 data &= ~mask; 81 data |= (value & mask); 82 83 writel(data, dwmac->regs + reg); 84 } 85 86 static int meson8b_init_clk(struct meson8b_dwmac *dwmac) 87 { > 88 struct clk_init_data init; 89 int i, ret; 90 struct device *dev = &dwmac->pdev->dev; 91 char clk_name[32]; 92 const char *clk_div_parents[1]; 93 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; > 94 static struct clk_div_table clk_25m_div_table[] = { > 95 { .val = 0, .div = 5 }, > 96 { .val = 1, .div = 10 }, 97 { /* sentinel */ }, 98 }; 99 100 /* get the mux parents from DT */ 101 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 102 char name[16]; 103 104 snprintf(name, sizeof(name), "clkin%d", i); 105 dwmac->m250_mux_parent[i] = devm_clk_get(dev, name); 106 if (IS_ERR(dwmac->m250_mux_parent[i])) { 107 ret = PTR_ERR(dwmac->m250_mux_parent[i]); 108 if (ret != -EPROBE_DEFER) 109 dev_err(dev, "Missing clock %s\n", name); 110 return ret; 111 } 112 > 113 mux_parent_names[i] = > 114 __clk_get_name(dwmac->m250_mux_parent[i]); 115 } 116 117 /* create the m250_mux */ 118 snprintf(clk_name, sizeof(clk_name), "%s#m250_sel", dev_name(dev)); 119 init.name = clk_name; > 120 init.ops = &clk_mux_ops; 121 init.flags = 0; 122 init.parent_names = mux_parent_names; 123 init.num_parents = MUX_CLK_NUM_PARENTS; 124 125 dwmac->m250_mux.reg = dwmac->regs + PRG_ETH0; 126 dwmac->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT; 127 dwmac->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK; 128 dwmac->m250_mux.flags = 0; 129 dwmac->m250_mux.table = NULL; 130 dwmac->m250_mux.hw.init = &init; 131 > 132 dwmac->m250_mux_clk = devm_clk_register(dev, &dwmac->m250_mux.hw); 133 if (WARN_ON(IS_ERR(dwmac->m250_mux_clk))) 134 return PTR_ERR(dwmac->m250_mux_clk); 135 136 /* create the m250_div */ 137 snprintf(clk_name, sizeof(clk_name), "%s#m250_div", dev_name(dev)); 138 init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL); > 139 init.ops = &clk_divider_ops; > 140 init.flags = CLK_SET_RATE_PARENT; > 141 clk_div_parents[0] = __clk_get_name(dwmac->m250_mux_clk); 142 init.parent_names = clk_div_parents; 143 init.num_parents = ARRAY_SIZE(clk_div_parents); 144 145 dwmac->m250_div.reg = dwmac->regs + PRG_ETH0; 146 dwmac->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT; 147 dwmac->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH; 148 dwmac->m250_div.hw.init = &init; > 149 dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; 150 151 dwmac->m250_div_clk = devm_clk_register(dev, &dwmac->m250_div.hw); 152 if (WARN_ON(IS_ERR(dwmac->m250_div_clk))) 153 return PTR_ERR(dwmac->m250_div_clk); 154 155 /* create the m25_div */ 156 snprintf(clk_name, sizeof(clk_name), "%s#m25_div", dev_name(dev)); 157 init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL); 158 init.ops = &clk_divider_ops; > 159 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; 160 clk_div_parents[0] = __clk_get_name(dwmac->m250_div_clk); 161 init.parent_names = clk_div_parents; 162 init.num_parents = ARRAY_SIZE(clk_div_parents); --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index 44b630c..f77edb9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -9,7 +9,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \ obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o -obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o +obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c new file mode 100644 index 0000000..a31ec24 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -0,0 +1,324 @@ +/* + * Amlogic Meson S805/S905 DWMAC glue layer + * + * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/ethtool.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/module.h> +#include <linux/of_net.h> +#include <linux/mfd/syscon.h> +#include <linux/platform_device.h> +#include <linux/stmmac.h> + +#include "stmmac_platform.h" + +#define PRG_ETH0 0x0 + +#define PRG_ETH0_RGMII_MODE BIT(0) + +/* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ +#define PRG_ETH0_CLK_M250_SEL_SHIFT 4 +#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) + +#define PRG_ETH0_TXDLY_SHIFT 5 +#define PRG_ETH0_TXDLY_MASK GENMASK(6, 5) +#define PRG_ETH0_TXDLY_OFF (0x0 << PRG_ETH0_TXDLY_SHIFT) +#define PRG_ETH0_TXDLY_QUARTER (0x1 << PRG_ETH0_TXDLY_SHIFT) +#define PRG_ETH0_TXDLY_HALF (0x2 << PRG_ETH0_TXDLY_SHIFT) +#define PRG_ETH0_TXDLY_THREE_QUARTERS (0x3 << PRG_ETH0_TXDLY_SHIFT) + +/* divider for the result of m250_sel */ +#define PRG_ETH0_CLK_M250_DIV_SHIFT 7 +#define PRG_ETH0_CLK_M250_DIV_WIDTH 3 + +/* divides the result of m25_sel by either 5 (bit unset) or 10 (bit set) */ +#define PRG_ETH0_CLK_M25_DIV_SHIFT 10 +#define PRG_ETH0_CLK_M25_DIV_WIDTH 1 + +#define PRG_ETH0_INVERTED_RMII_CLK BIT(11) +#define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) + +#define MUX_CLK_NUM_PARENTS 2 + +struct meson8b_dwmac { + struct platform_device *pdev; + + void __iomem *regs; + + phy_interface_t phy_mode; + + struct clk_mux m250_mux; + struct clk *m250_mux_clk; + struct clk *m250_mux_parent[MUX_CLK_NUM_PARENTS]; + + struct clk_divider m250_div; + struct clk *m250_div_clk; + + struct clk_divider m25_div; + struct clk *m25_div_clk; +}; + +static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, + u32 mask, u32 value) +{ + u32 data; + + data = readl(dwmac->regs + reg); + data &= ~mask; + data |= (value & mask); + + writel(data, dwmac->regs + reg); +} + +static int meson8b_init_clk(struct meson8b_dwmac *dwmac) +{ + struct clk_init_data init; + int i, ret; + struct device *dev = &dwmac->pdev->dev; + char clk_name[32]; + const char *clk_div_parents[1]; + const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; + static struct clk_div_table clk_25m_div_table[] = { + { .val = 0, .div = 5 }, + { .val = 1, .div = 10 }, + { /* sentinel */ }, + }; + + /* get the mux parents from DT */ + for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { + char name[16]; + + snprintf(name, sizeof(name), "clkin%d", i); + dwmac->m250_mux_parent[i] = devm_clk_get(dev, name); + if (IS_ERR(dwmac->m250_mux_parent[i])) { + ret = PTR_ERR(dwmac->m250_mux_parent[i]); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Missing clock %s\n", name); + return ret; + } + + mux_parent_names[i] = + __clk_get_name(dwmac->m250_mux_parent[i]); + } + + /* create the m250_mux */ + snprintf(clk_name, sizeof(clk_name), "%s#m250_sel", dev_name(dev)); + init.name = clk_name; + init.ops = &clk_mux_ops; + init.flags = 0; + init.parent_names = mux_parent_names; + init.num_parents = MUX_CLK_NUM_PARENTS; + + dwmac->m250_mux.reg = dwmac->regs + PRG_ETH0; + dwmac->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT; + dwmac->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK; + dwmac->m250_mux.flags = 0; + dwmac->m250_mux.table = NULL; + dwmac->m250_mux.hw.init = &init; + + dwmac->m250_mux_clk = devm_clk_register(dev, &dwmac->m250_mux.hw); + if (WARN_ON(IS_ERR(dwmac->m250_mux_clk))) + return PTR_ERR(dwmac->m250_mux_clk); + + /* create the m250_div */ + snprintf(clk_name, sizeof(clk_name), "%s#m250_div", dev_name(dev)); + init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL); + init.ops = &clk_divider_ops; + init.flags = CLK_SET_RATE_PARENT; + clk_div_parents[0] = __clk_get_name(dwmac->m250_mux_clk); + init.parent_names = clk_div_parents; + init.num_parents = ARRAY_SIZE(clk_div_parents); + + dwmac->m250_div.reg = dwmac->regs + PRG_ETH0; + dwmac->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT; + dwmac->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH; + dwmac->m250_div.hw.init = &init; + dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; + + dwmac->m250_div_clk = devm_clk_register(dev, &dwmac->m250_div.hw); + if (WARN_ON(IS_ERR(dwmac->m250_div_clk))) + return PTR_ERR(dwmac->m250_div_clk); + + /* create the m25_div */ + snprintf(clk_name, sizeof(clk_name), "%s#m25_div", dev_name(dev)); + init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL); + init.ops = &clk_divider_ops; + init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; + clk_div_parents[0] = __clk_get_name(dwmac->m250_div_clk); + init.parent_names = clk_div_parents; + init.num_parents = ARRAY_SIZE(clk_div_parents); + + dwmac->m25_div.reg = dwmac->regs + PRG_ETH0; + dwmac->m25_div.shift = PRG_ETH0_CLK_M25_DIV_SHIFT; + dwmac->m25_div.width = PRG_ETH0_CLK_M25_DIV_WIDTH; + dwmac->m25_div.table = clk_25m_div_table; + dwmac->m25_div.hw.init = &init; + dwmac->m25_div.flags = CLK_DIVIDER_ALLOW_ZERO; + + dwmac->m25_div_clk = devm_clk_register(dev, &dwmac->m25_div.hw); + if (WARN_ON(IS_ERR(dwmac->m25_div_clk))) + return PTR_ERR(dwmac->m25_div_clk); + + return 0; +} + +static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) +{ + int ret; + unsigned long clk_rate; + + switch (dwmac->phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Generate a 25MHz clock for the PHY */ + clk_rate = 25 * 1000 * 1000; + + /* enable RGMII mode */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, + PRG_ETH0_RGMII_MODE); + + /* only relevant for RMII mode -> disable in RGMII mode */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_INVERTED_RMII_CLK, 0); + + /* TX clock delay - all known boards use a 1/4 cycle delay */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, + PRG_ETH0_TXDLY_QUARTER); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Use the rate of the mux clock for the internal RMII PHY */ + clk_rate = clk_get_rate(dwmac->m250_mux_clk); + + /* disable RGMII mode -> enables RMII mode */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, + 0); + + /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_INVERTED_RMII_CLK, + PRG_ETH0_INVERTED_RMII_CLK); + + /* TX clock delay cannot be configured in RMII mode */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, + 0); + + break; + + default: + dev_err(&dwmac->pdev->dev, "unsupported phy-mode %s\n", + phy_modes(dwmac->phy_mode)); + return -EINVAL; + } + + ret = clk_prepare_enable(dwmac->m25_div_clk); + if (ret) { + dev_err(&dwmac->pdev->dev, "failed to enable the PHY clock\n"); + return ret; + } + + ret = clk_set_rate(dwmac->m25_div_clk, clk_rate); + if (ret) { + clk_disable_unprepare(dwmac->m25_div_clk); + + dev_err(&dwmac->pdev->dev, "failed to set PHY clock\n"); + return ret; + } + + /* enable TX_CLK and PHY_REF_CLK generator */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK, + PRG_ETH0_TX_AND_PHY_REF_CLK); + + return 0; +} + +static int meson8b_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct resource *res; + struct meson8b_dwmac *dwmac; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); + if (!dwmac) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dwmac->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dwmac->regs)) + return PTR_ERR(dwmac->regs); + + dwmac->pdev = pdev; + dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node); + if (dwmac->phy_mode < 0) { + dev_err(&pdev->dev, "missing phy-mode property\n"); + return -EINVAL; + } + + ret = meson8b_init_clk(dwmac); + if (ret) + return ret; + + ret = meson8b_init_prg_eth(dwmac); + if (ret) + return ret; + + plat_dat->bsp_priv = dwmac; + + return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); +} + +static int meson8b_dwmac_remove(struct platform_device *pdev) +{ + struct meson8b_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev); + + clk_disable_unprepare(dwmac->m25_div_clk); + + return stmmac_pltfr_remove(pdev); +} + +static const struct of_device_id meson8b_dwmac_match[] = { + { .compatible = "amlogic,meson8b-dwmac" }, + { .compatible = "amlogic,meson-gxbb-dwmac" }, + { } +}; +MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); + +static struct platform_driver meson8b_dwmac_driver = { + .probe = meson8b_dwmac_probe, + .remove = meson8b_dwmac_remove, + .driver = { + .name = "meson8b-dwmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = meson8b_dwmac_match, + }, +}; +module_platform_driver(meson8b_dwmac_driver); + +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); +MODULE_DESCRIPTION("Amlogic Meson S805/S905 DWMAC glue layer"); +MODULE_LICENSE("GPL v2");

[v4,4/5] net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC

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