From patchwork Mon Nov 7 00:13:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Moritz Fischer X-Patchwork-Id: 9414203 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 49EBC60720 for ; Mon, 7 Nov 2016 00:16:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C26028EB9 for ; Mon, 7 Nov 2016 00:16:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 309AC28EBA; Mon, 7 Nov 2016 00:16:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8563C28EBE for ; Mon, 7 Nov 2016 00:16:21 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1c3Xa7-0004RG-7X; Mon, 07 Nov 2016 00:14:35 +0000 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1c3XZY-0004KU-CC for linux-arm-kernel@lists.infradead.org; Mon, 07 Nov 2016 00:14:02 +0000 Received: by mail-pf0-x233.google.com with SMTP id 189so81582102pfz.3 for ; Sun, 06 Nov 2016 16:13:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ettus-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ggZLFjixydSPYhBD39KoC+ZVr813kLw2TjJOCBX062Y=; b=subemfbD5sLqgWYONg3+OElnUYVdIM6N02Jc8wpUBiXTCryQnQnURErOA19y8U2dsT J9EIjuudjYRrH605z4N+5fW7Npj0ApDPpdKGmwCgJ+RPQ1Nl4Y/RIaecvlbNUodCGr0n 4b3JgoH68KbAD3DR3GlEP1xMO1St+Dn1ylqxJIwc6nZU/MCa+izKbUYXl0q5UhAB6AS0 n2AIRnoyyIbYFunDoZlwDEIM7+tFVh7PvK1hq45MIulWR1aTY+jtgPJpAgSKX78n5ur9 zqVsH6vTixgR+4aO6kTq+nisDAluCQBvFnzrx4+WoEAuCKkO3KKCumAvlf+XIV2sBhIS sNOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ggZLFjixydSPYhBD39KoC+ZVr813kLw2TjJOCBX062Y=; b=jTPHtd+wlse2ZFfBi+nHmDGy5Zg0ismPrZwefUie7SegXEG1MW+03fWxeuMp21NJ2c 4HL1joPE/OBVH6taJEKhZQqddrnZmr+fD9O6JZi+xxY48LrP5qL0y1Pu71e3upEJUmiU AhhDNK5zaM6d3vOaf6PCVzx2ev6JfOM90UEgGioEPnhD+uvUYXSWEhMLyR+ohPp8f4yN Z8nRWEIKtxmFz/57HkxOFIMtHQyuzxdVVZd8H2ce4jpTHab+WATbBBhGV7e5gciw2+xm fl0mAFSjEiFom8HbEcFtB6Ab79YBGRRjcbEaaApJktbjxnGkARFXXXZ4o4mc40PnH/VR pAjQ== X-Gm-Message-State: ABUngvdjAGHkxi2TEeKDTYyom6h9nrxYkymEFf1F1e49KLwHaGu7SmSzFgFgc49lyqblLq6e X-Received: by 10.99.176.77 with SMTP id z13mr6631312pgo.158.1478477619297; Sun, 06 Nov 2016 16:13:39 -0800 (PST) Received: from archbook.lan ([2601:647:4b00:de01::921]) by smtp.gmail.com with ESMTPSA id t5sm35117798pfb.58.2016.11.06.16.13.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 06 Nov 2016 16:13:38 -0800 (PST) From: Moritz Fischer To: linux-kernel@vger.kernel.org Subject: [PATCH 1/4] fpga mgr: Introduce FPGA capabilities Date: Sun, 6 Nov 2016 17:13:23 -0700 Message-Id: <20161107001326.7395-2-moritz.fischer@ettus.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20161107001326.7395-1-moritz.fischer@ettus.com> References: <20161107001326.7395-1-moritz.fischer@ettus.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161106_161400_542238_4B345201 X-CRM114-Status: GOOD ( 16.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Moritz Fischer , julia@ni.com, atull@opensource.altera.com, michal.simek@xilinx.com, soren.brinkmann@xilinx.com, moritz.fischer.private@gmail.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add FPGA capabilities as a way to express the capabilities of a given FPGA manager. Removes code duplication by comparing the low-level driver's capabilities at the framework level rather than having each driver check for supported operations in the write_init() callback. This allows for extending with additional capabilities, similar to the the dmaengine framework's implementation. Signed-off-by: Moritz Fischer Cc: Alan Tull Cc: Michal Simek Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org --- Changes from RFC: * in the RFC the caps weren't actually stored into the struct fpga_mgr Note: If people disagree on the typedef being a 'false positive' I can fix that in a future rev of the patchset. Thanks, Moritz --- drivers/fpga/fpga-mgr.c | 15 ++++++++++++++ drivers/fpga/socfpga.c | 10 +++++----- drivers/fpga/zynq-fpga.c | 7 ++++++- include/linux/fpga/fpga-mgr.h | 46 ++++++++++++++++++++++++++++++++++++++++++- 4 files changed, 71 insertions(+), 7 deletions(-) diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index 953dc91..ed57c17 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -49,6 +49,18 @@ int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags, const char *buf, struct device *dev = &mgr->dev; int ret; + if (flags & FPGA_MGR_PARTIAL_RECONFIG && + !fpga_mgr_has_cap(FPGA_MGR_CAP_PARTIAL_RECONF, mgr->caps)) { + dev_err(dev, "Partial reconfiguration not supported\n"); + return -ENOTSUPP; + } + + if (flags & FPGA_MGR_FULL_RECONFIG && + !fpga_mgr_has_cap(FPGA_MGR_CAP_FULL_RECONF, mgr->caps)) { + dev_err(dev, "Full reconfiguration not supported\n"); + return -ENOTSUPP; + } + /* * Call the low level driver's write_init function. This will do the * device-specific things to get the FPGA into the state where it is @@ -245,12 +257,14 @@ EXPORT_SYMBOL_GPL(fpga_mgr_put); * @dev: fpga manager device from pdev * @name: fpga manager name * @mops: pointer to structure of fpga manager ops + * @caps: fpga manager capabilities * @priv: fpga manager private data * * Return: 0 on success, negative error code otherwise. */ int fpga_mgr_register(struct device *dev, const char *name, const struct fpga_manager_ops *mops, + fpga_mgr_cap_mask_t caps, void *priv) { struct fpga_manager *mgr; @@ -282,6 +296,7 @@ int fpga_mgr_register(struct device *dev, const char *name, mgr->name = name; mgr->mops = mops; mgr->priv = priv; + mgr->caps = caps; /* * Initialize framework state by requesting low level driver read state diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 27d2ff2..fd9760c 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -413,10 +413,6 @@ static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr, u32 flags, struct socfpga_fpga_priv *priv = mgr->priv; int ret; - if (flags & FPGA_MGR_PARTIAL_RECONFIG) { - dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); - return -EINVAL; - } /* Steps 1 - 5: Reset the FPGA */ ret = socfpga_fpga_reset(mgr); if (ret) @@ -555,6 +551,7 @@ static int socfpga_fpga_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct socfpga_fpga_priv *priv; struct resource *res; + fpga_mgr_cap_mask_t caps; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -580,8 +577,11 @@ static int socfpga_fpga_probe(struct platform_device *pdev) if (ret) return ret; + fpga_mgr_cap_zero(&caps); + fpga_mgr_cap_set(FPGA_MGR_CAP_FULL_RECONF, caps); + return fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager", - &socfpga_fpga_ops, priv); + &socfpga_fpga_ops, caps, priv); } static int socfpga_fpga_remove(struct platform_device *pdev) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index c2fb412..1d37ff0 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -410,6 +410,7 @@ static int zynq_fpga_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct zynq_fpga_priv *priv; struct resource *res; + fpga_mgr_cap_mask_t caps; int err; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -461,9 +462,13 @@ static int zynq_fpga_probe(struct platform_device *pdev) zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK); clk_disable(priv->clk); + fpga_mgr_cap_zero(&caps); + fpga_mgr_cap_set(FPGA_MGR_CAP_FULL_RECONF, caps); + fpga_mgr_cap_set(FPGA_MGR_CAP_PARTIAL_RECONF, caps); + err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager", - &zynq_fpga_ops, priv); + &zynq_fpga_ops, caps, priv); if (err) { dev_err(dev, "unable to register FPGA manager"); clk_unprepare(priv->clk); diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 0940bf4..e73429c 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -67,6 +67,47 @@ enum fpga_mgr_states { * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported */ #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) +#define FPGA_MGR_FULL_RECONFIG BIT(1) + +enum fpga_mgr_capability { + FPGA_MGR_CAP_PARTIAL_RECONF, + FPGA_MGR_CAP_FULL_RECONF, + +/* last capability type for creation of the capabilities mask */ + FPGA_MGR_CAP_END, +}; + +typedef struct { DECLARE_BITMAP(bits, FPGA_MGR_CAP_END); } fpga_mgr_cap_mask_t; + +#define fpga_mgr_has_cap(cap, mask) __fpga_mgr_has_cap((cap), &(mask)) +static inline int __fpga_mgr_has_cap(enum fpga_mgr_capability cap, + fpga_mgr_cap_mask_t *mask) +{ + return test_bit(cap, mask->bits); +} + +#define fpga_mgr_cap_zero(mask) __fpga_mgr_cap_zero(mask) +static inline void __fpga_mgr_cap_zero(fpga_mgr_cap_mask_t *mask) +{ + bitmap_zero(mask->bits, FPGA_MGR_CAP_END); +} + +#define fpga_mgr_cap_clear(cap, mask) __fpga_mgr_cap_clear((cap), &(mask)) +static inline void __fpga_mgr_cap_clear(enum fpga_mgr_capability cap, + fpga_mgr_cap_mask_t *mask) + +{ + clear_bit(cap, mask->bits); +} + +#define fpga_mgr_cap_set(cap, mask) __fpga_mgr_cap_set((cap), &(mask)) +static inline void __fpga_mgr_cap_set(enum fpga_mgr_capability cap, + fpga_mgr_cap_mask_t *mask) + +{ + set_bit(cap, mask->bits); +} + /** * struct fpga_manager_ops - ops for low level fpga manager drivers @@ -105,6 +146,7 @@ struct fpga_manager { enum fpga_mgr_states state; const struct fpga_manager_ops *mops; void *priv; + fpga_mgr_cap_mask_t caps; }; #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev) @@ -120,7 +162,9 @@ struct fpga_manager *of_fpga_mgr_get(struct device_node *node); void fpga_mgr_put(struct fpga_manager *mgr); int fpga_mgr_register(struct device *dev, const char *name, - const struct fpga_manager_ops *mops, void *priv); + const struct fpga_manager_ops *mops, + fpga_mgr_cap_mask_t caps, + void *priv); void fpga_mgr_unregister(struct device *dev);