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[2.108.209.202]) by smtp.gmail.com with ESMTPSA id 29sm7578325lft.43.2016.12.10.12.47.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 10 Dec 2016 12:47:06 -0800 (PST) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Subject: [RFC PATCH 1/7] arm64: Use physical counter for in-kernel reads Date: Sat, 10 Dec 2016 21:47:06 +0100 Message-Id: <20161210204712.21830-2-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20161210204712.21830-1-christoffer.dall@linaro.org> References: <20161210204712.21830-1-christoffer.dall@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161210_124729_133976_17F65C2E X-CRM114-Status: GOOD ( 12.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Christoffer Dall MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Using the physical counter allows KVM to retain the offset between the virtual and physical counter as long as it is actively running a VCPU. As soon as a VCPU is released, another thread is scheduled or we start running userspace applications, we reset the offset to 0, so that VDSO operations can still read the virtual counter and get the same view of time as the kernel. This opens up potential improvements for KVM performance. VHE kernels or kernels using the virtual timer are unaffected by this. Signed-off-by: Christoffer Dall --- arch/arm64/include/asm/arch_timer.h | 6 ++++-- drivers/clocksource/arm_arch_timer.c | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index eaa5bbe..cec2549 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -139,11 +139,13 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl) static inline u64 arch_counter_get_cntpct(void) { + u64 cval; /* * AArch64 kernel and user space mandate the use of CNTVCT. */ - BUG(); - return 0; + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cval)); + return cval; } static inline u64 arch_counter_get_cntvct(void) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 73c487d..a5b0789 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -597,7 +597,7 @@ static void __init arch_counter_register(unsigned type) /* Register the CP15 based counter if we have one */ if (type & ARCH_CP15_TIMER) { - if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI) + if (arch_timer_uses_ppi == VIRT_PPI || is_kernel_in_hyp_mode()) arch_timer_read_counter = arch_counter_get_cntvct; else arch_timer_read_counter = arch_counter_get_cntpct;